Resource-constrained Applications Research Articles

A New Pairing-Free Certificateless Signcryption Scheme

Signcryption is a cryptographic primitive which provides unforgeability and confidentiality for digital communications. Many signcryption schemes have been constructed in the literature for secure communication between smart objects. But, many of these existing schemes are not secure and inefficient for resource constrained applications like WSNs, Mobile computing, VANETs and IoT applications. To enrich the security and efficiency issues, in this paper, we propose a new signcryption scheme in certificateless based framework and prove its security under the CDHP and ECDLP assumptions. The efficiency analysis indicates that our scheme is more efficient than other existing signcryption schemes and is well suitable for resource-constrained applications.

RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference

Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an open-source instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to reduce the computational overhead at the HD inference phase, we introduce a pruning method to remove the ineffectual dimensions. The proposed pruning method can reduce the dimension from 10k to 1k with negligible accuracy loss. Second, an ISA extension for RI5CY is proposed to compute the HD inference efficiently. Experimental results indicate that RISC-HD adds <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.42\times $ </tex-math></inline-formula> area overhead to the RI5CY core; however, it consumes only 2932 slices on the Artix-7 FPGA, which is suitable for resource-constrained devices. Additionally, RISC-HD improves the total clock cycle by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.48\times $ </tex-math></inline-formula> compared to the RI5CY core and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.17\times $ </tex-math></inline-formula> compared to ARM Cortex-M4 in the ISOLET data set. Moreover, RISC-HD achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.22\times $ </tex-math></inline-formula> energy efficiency compared to the RI5CY core.

Efficient hardware implementations of lightweight Simeck Cipher for resource-constrained applications

Due to the vigorous and ever-evolving demands of the IoT field, resource-constrained devices are being deployed in such areas and several new challenges like sequestration and surveillance, have come into the picture. Multiple lightweight designs have been recommended to overcome the security issues for resource-constrained devices. In applications requiring data to be transmitted fast between various devices, loop unrolling and subsequent pipelining architectures are extremely efficient. In this paper, several efficient hardware implementations of Simeck cipher such as loop unrolling architecture and outer round pipelining technique have been proposed in order to achieve high throughput. This paper has also proposed a bit serialized architecture of the Simeck cipher that reduces the area footprint and used in less resource applications. Our Simeck Serial architecture is 29.5 times more efficient than LiCi cipher and occupies only 7% of the area occupied by LiCi cipher. Similarly, our proposed serial architecture occupies only 13% and 25% of total slices occupied by X192 and XTEA respectively while still performs 184% and 161% more efficiently. All three architectures are evaluated and compared on the basis of throughput, area utilization, and power consumption for their implementations in different FPGA platforms.

A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic

Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.35\times $ </tex-math></inline-formula> power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications.

Square-Root Robocentric Visual-Inertial Odometry With Online Spatiotemporal Calibration

Robocentric visual-inertial odometry (R-VIO) in our recent work [1] models the probabilistic state estimation problem with respect to a moving local (body) frame, which is contrary to a fixed global (world) frame as in the world-centric formulation, thus avoiding the observability mismatch issue and achieving better estimation consistency. To further improve efficiency and robustness in order to be amenable for the resource-constrained applications, in this paper, we propose a novel information-based estimator, termed R-VIO2. In particular, the numerical stability and computational efficiency are significantly boosted by using i) the square-root expression and ii) incremental QR-based update combined with back substitution. Moreover, the spatial transformation and time offset between visual and inertial sensors are jointly calibrated online to robustify the estimator performance in the presence of unknown parameter errors. The proposed R-VIO2 has been extensively tested on public benchmark dataset as well as in a large-scale real-world experiment, and shown to achieve very competitive accuracy and superior time efficiency against the state-of-the-art visual-inertial navigation methods.

A Multifunctional 3D Bioprinting System for Construction of Complex Tissue Structure Scaffolds: Design and Application.

Three-dimensional (3D) bioprinting offers a potentially powerful new approach to reverse engineering human pathophysiology to address the problem of developing more biomimetic experimental systems. Human tissues and organs are multiscale and multi-material structures. The greatest challenge for organ printing is the complexity of the structural elements, from the shape of the macroscopic structure to the details of the nanostructure. A highly bionic tissue-organ model requires the use of multiple printing processes. Some printers with multiple nozzles and multiple processes are currently reported. However, the bulk volume, which is inconvenient to move, and the high cost of these printing systems limits the expansion of their applications. Scientists urgently need a multifunctional miniaturized 3D bioprinter. In this study, a portable multifunctional 3D bioprinting system was built based on a modular design and a custom written operating application. Using this platform, constructs with detailed surface structures, hollow structures, and multiscale complex tissue analogs were successfully printed using commercial polymers and a series of hydrogel-based inks. With further development, this portable, modular, low-cost, and easy-to-use Bluetooth-enabled 3D printer promises exciting opportunities for resource-constrained application scenarios, not only in biomedical engineering but also in the education field, and may be used in space experiments.

A Bio-Inspired Hierarchical Spiking Neural Network With Reward-Modulated STDP Learning Rule for AER Object Recognition

The inherent spike-based and event-driven computation makes spiking neural networks (SNNs) naturally suitable to provide efficient and low-latency solution in neuromorphic vision processing. In this work we propose an address-event representation (AER) object recognition system which consists of a noise filter, an event stream segmentation module and a hierarchical convolutional SNN. In order to improve the feature learning capacity of bio-inspired shallow hierarchical SNNs for AER object recognition, we apply a convolutional SNN with R-STDP learning rule and first-spike coding to further extract features after primary feature learning using Gabor filter-based event-driven convolution. The R-STDP learning rule enables the network to adjust weights by combining local STDP learning rule with a global reward signal and to make classification without using an external classifier. Experimental results show that our method significantly outperforms the existing hierarchical SNN-based recognition methods on four popular AER datasets. Moreover, our method has much better recognition ability when using very short input event stream, and can effectively learn from small size training sets. In addition, the robustness of the network to input noise is improved. Our method is very beneficial for developing neuromorphic-vision object recognition algorithm in resource-constrained applications when event streams are short and training samples are limited.

A Brief Review of Deep Neural Network Implementations for ARM Cortex-M Processor

Deep neural networks have recently become increasingly used for a wide range of applications, (e.g., image and video processing). The demand for edge inference is growing, especially in the areas of relevance to the Internet-of-Things. Low-cost microcontrollers as edge devices are a promising solution for optimal application systems from several points of view such as: cost, power consumption, latency, or real-time execution. The implementation of these systems has become feasible due to the advanced development of hardware architectures and DSP capabilities, while the cost and power consumption have been maintained at a low level. The aim of the paper is to provide a literature review on the implementation of deep neural networks using ARM Cortex-M core-based low-cost microcontrollers. As an emerging research direction, there are a limited number of publications that address this topic at the moment. Therefore, the research papers that stand out have been analyzed in greater detail, to promote further interest of researchers to bring AI techniques to low power standard ARM Cortex-M microcontrollers. The article addresses a niche research domain. Despite the increasing interest manifested toward both (1) edge AI applications and (2) theoretical contributions in DNN optimization and compression, the number of existing publications dedicated to the current topic is rather limited. Therefore, a comprehensive literature survey using systematic mapping is not possible. The presentation focuses on systems that have shown increased efficiency in resource-constrained applications, as well as the predominant impediments that still hinder their implementation. The reader will take away the following concepts from this paper: (1) an overview of applications, DNN architectures, and results obtained using ARM Cortex-M core-based microcontrollers, (2) an overview of low-cost hardware devices and SW development solutions, and (3) understanding recent trends and opportunities.

Lightweight CNN-based malware image classification for resource-constrained applications

Lightweight CNN-based malware image classification for resource-constrained applications

Low-Complexity Adaptive Sampling of Block Compressed Sensing Based on Distortion Minimization.

Block compressed sensing (BCS) is suitable for image sampling and compression in resource-constrained applications. Adaptive sampling methods can effectively improve the rate-distortion performance of BCS. However, adaptive sampling methods bring high computational complexity to the encoder, which loses the superiority of BCS. In this paper, we focus on improving the adaptive sampling performance at the cost of low computational complexity. Firstly, we analyze the additional computational complexity of the existing adaptive sampling methods for BCS. Secondly, the adaptive sampling problem of BCS is modeled as a distortion minimization problem. We present three distortion models to reveal the relationship between block sampling rate and block distortion and use a simple neural network to predict the model parameters from several measurements. Finally, a fast estimation method is proposed to allocate block sampling rates based on distortion minimization. The results demonstrate that the proposed estimation method of block sampling rates is effective. Two of the three proposed distortion models can make the proposed estimation method have better performance than the existing adaptive sampling methods of BCS. Compared with the calculation of BCS at the sampling rate of 0.1, the additional calculation of the proposed adaptive sampling method is less than 1.9%.

Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization

Lightweight cryptography provides security to resource-constrained applications, such as embedded systems and Internet of Things (IoT) devices. This work explores an ultra-lightweight implementation of RC5 block cipher, via two levels of serialization. We also exploit a resource-sharing optimization technique for the data-dependent rotation (DDR) module, since it is the most computationally intensive component of the RC5 block cipher. We present two RC5 hardware structures: (i) an 8-bit serial RC5 architecture using a dual-part DDR unit; this design occupies only 54 slices on a Spartan-6 FPGA device and is 69% superior in terms of Throughput-per-Slice (TPS) compared to the smallest 8-bit AES FPGA implementation, (ii) a novel bit-serial RC5 architecture based on shift-register LUT (SRL) primitives; this design consumes only 20 Spartan-6 slices and shows 81% improvement in throughput performance at the expense of only 5% additional area resources compared to the smallest bit-serial AES design reported. The proposed DDR-based optimizations and efficient time scheduling make our proposed designs outperform most of the state-of-the-art lightweight block cipher designs in terms of hardware efficiency (with regard to TPS).

Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA

In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays an essential role in many security applications, such as transport layer security (TLS), internet protocol security (IPsec), and wireless sensor networks (WSNs). The proposed designs of ECC hardware implementation only focus on a single ECC variant and use many resources. These proposals cannot be used for resource-constrained applications or for the devices that need to provide multiple levels of security. This work provides a multi-functional elliptic curve digital signature algorithm (ECDSA) and Edwards-curve digital signature algorithm (EdDSA) hardware implementation. The core can run multiple ECDSA/EdDSA algorithms in a single design. The design consumes fewer resources than the other single-functional design, and is not based on digital signal processors (DSP). The experiments show that the proposed core could run up to 112.2 megahertz with Virtex-7 devices while consuming only 10,259 slices in total.

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

Clock is the most important signal in electronic system. In current practice, the dominant clocking style is the fixed-frequency approach. For a given application, the clock signal is only required to work at a few selected frequencies. Moreover, in the process of performing a task, it must not change its frequency. This style has worked well in the past. However, it is preventing information processing efficiency from being raised to next level. Worse yet, the emergence of resource-constrained applications, such as edge computing and IoT, can render this approach unserviceable. In this paper, a new perspective of flexible clocking ideology is advocated. It promotes the use of a clock generator, TAF-DPS, that possesses features of “arbitrary frequency generation” and “instantaneous frequency switching”. Owing to its superior capability in synthesizing waveform, TAF-DPS can handle many signal processing problems in a more elegant manner and serve some special purposes more efficiently. Further, it can be used for generating data for security purposes. TAF-DPS is especially valuable for environments with large frequency instability, which is a major problem in resource-constrained applications. The contribution of this paper is the advocacy of a new perspective of flexible clocking. This ideology is gradually developed in this paper as the argument is carried out through examples of novel architectures enabled by TAF-DPS. The perspective naturally emerges from the collective effect of those novel architectures. The large number of emerging applications, exemplified by edge computing and IoT, inspire system-level innovations that inevitably present new challenges to circuit-level. Those challenges are so demanding that they require overhaul in our circuit design philosophy. This new perspective is such an overhaul in fundamental level. Its aim is to answer the challenges, for better serving the emerging demands in higher levels.

Learning-Free Hyperspectral Anomaly Detection With Unpredictive Frequency Residual Priors

Hyperspectral anomaly detection aims to fast and credibly find nontrivial candidate targets without prior knowledge, which has become an increasingly pressing need as imagery swath and resolution are growing rapidly. Relevant state-of-the-art learning-based anomaly detection approaches have benefited from data-driven hierarchical feature embeddings that typically model the geometric distribution of spectral vectors. However, most of these techniques are incompatible with resource-constrained applications: 1) huge computational costs caused by feedforward convolution operation cannot be supported with limited computation resources and storage (e.g., in-orbit processing); 2) detection accuracy relies on large-scale training datasets, which results in labor-expensive imagery collection, pixel-level labeling, and time-consuming learning procedure. To address these issues, we advocate a learning-free, frequency domain anomaly detection method combined with predictive coding, an intriguing heuristic prior from human vision system. Technically, 1) inherently efficient frequency transformation could be implemented with existing image compression modules (e.g., JPEG or JPEG2000 codec), which improves the utilization of computational resources; 2) predictive coding mechanism is exploited for suppressing frequently occurring information represented in the low-entropy frequency domain, such that the “unpredictive” subject (i.e., anomaly spectrums) can “pop out” with naive residuals. Such heuristic prior incorporated into the computational model can reduce dependence on the large-scale training set. Experiments on real-world hyperspectral datasets confirm the efficacy of our model. Besides, low computation cost of the proposed (fast frequency transformation and analytical solutions) anomaly detector facilitates rather straightforward sliding window verification in high-resolution imagery.

Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator

Significant innovation has been made in the development of public-key cryptography that is able to withstand quantum attacks, known as post-quantum cryptography (PQC). This paper focuses on the development of an efficient PQC hardware implementation. Specifically, an implementation of the binary Ring-learning-with-errors (BRLWE)-based encryption scheme, a promising lightweight PQC suitable for resource-constrained applications, is proposed. The paper first develops the mathematical formulation to present the proposed algorithmic process. The corresponding hardware accelerators are then described in detail. Finally, comparisons with previous implementations are provided to demonstrate the superior performance of the proposed design. For instance, the proposed low-complexity accelerator has 34.7% less area-delay product (ADP) than the state-of-the-art design for <inline-formula><tex-math notation="LaTeX">$n=256$</tex-math></inline-formula> in the field-programmable gate array (FPGA) platform. Apart from the efficiency of the hardware architectures, the proposed design also has a complete input/output processing setup, and thus is feasible for emerging lightweight applications.

Constraint-based Diversification of JOP Gadgets

Modern software deployment process produces software that is uniform, and hence vulnerable to large-scale code-reuse attacks, such as Jump-Oriented Programming (JOP) attacks. Compiler-based diversification improves the resilience and security of software systems by automatically generating different assembly code versions of a given program. Existing techniques are efficient but do not have a precise control over the quality, such as the code size or speed, of the generated code variants. &#x0D; This paper introduces Diversity by Construction (DivCon), a constraint-based compiler approach to software diversification. Unlike previous approaches, DivCon allows users to control and adjust the conflicting goals of diversity and code quality. A key enabler is the use of Large Neighborhood Search (LNS) to generate highly diverse assembly code efficiently. For larger problems, we propose a combination of LNS with a structural decomposition of the problem. To further improve the diversification efficiency of DivCon against JOP attacks, we propose an application-specific distance measure tailored to the characteristics of JOP attacks. &#x0D; We evaluate DivCon with 20 functions from a popular benchmark suite for embedded systems. These experiments show that DivCon's combination of LNS and our application-specific distance measure generates binary programs that are highly resilient against JOP attacks (they share between 0.15% to 8% of JOP gadgets) with an optimality gap of 10%. Our results confirm that there is a trade-off between the quality of each assembly code version and the diversity of the entire pool of versions. In particular, the experiments show that DivCon is able to generate binary programs that share a very small number of gadgets, while delivering near-optimal code. &#x0D; For constraint programming researchers and practitioners, this paper demonstrates that LNS is a valuable technique for finding diverse solutions. For security researchers and software engineers, DivCon extends the scope of compiler-based diversification to performance-critical and resource-constrained applications.

Adaptive Artificial Intelligence for Resource-Constrained Connected Vehicles in Cybertwin-Driven 6G Network

The emerging technology of cybertwin is expected to bring revolutionary benefits to the sixth-generation (6G) network in respect of communication, resources allocation, and digital asset management. Empowered by ubiquitous artificial intelligence (AI), cybertwin is capable of adjusting the requests for computing resources to support network services by analyzing user’s demands for quality of experience and resource scarcity in the market. For resource-constrained applications, such as connected vehicles in the 6G network, cybertwin can intelligently determine the time-varying requests of computing resources for various vehicles at different times. However, the current service architecture executes AI algorithms with universal configurations for all vehicles. This causes the difficulty of customizing the complexity of AI algorithms to maintain adaptive to cybertwin’s decisions on dynamic resources allocation. In this article, we propose an adaptive AI framework based on efficient feature selection to cooperate with cybertwin’s resource allocation. This proposed framework can adaptively customizing AI model complexity with available computing resources. Specifically, we systematically characterize the aggregated impacts of all feature combinations on the modeling outcomes of AI algorithms. By utilizing nonadditive measures, the interactions among features can be quantified to indicate their contributions to the modeling process. Then, we propose an efficient algorithm to obtain accurate interaction measures for adaptive feature selection to balance the tradeoff between modeling accuracy and computational overhead. Finally, extensive simulations are conducted to validate that our proposed framework substantially reduces the overhead of AI algorithms while guaranteeing desired modeling accuracy for cybertwin-driven connected vehicles in 6G.

Double-Shift: A Low-Power DNN Weights Storage and Access Framework based on Approximate Decomposition and Quantization

One major challenge in deploying Deep Neural Network (DNN) in resource-constrained applications, such as edge nodes, mobile embedded systems, and IoT devices, is its high energy cost. The emerging approximate computing methodology can effectively reduce the energy consumption during the computing process in DNN. However, a recent study shows that the weight storage and access operations can dominate DNN's energy consumption due to the fact that the huge size of DNN weights must be stored in the high-energy-cost DRAM. In this paper, we propose Double-Shift, a low-power DNN weight storage and access framework, to solve this problem. Enabled by approximate decomposition and quantization, Double-Shift can reduce the data size of the weights effectively. By designing a novel weight storage allocation strategy, Double-Shift can boost the energy efficiency by trading the energy consuming weight storage and access operations for low-energy-cost computations. Our experimental results show that Double-Shift can reduce DNN weights to 3.96%–6.38% of the original size and achieve an energy saving of 86.47%–93.62%, while introducing a DNN classification error within 2%.

A General Rate-Distortion Optimization Method for Block Compressed Sensing of Images.

Block compressed sensing (BCS) is a promising technology for image sampling and compression for resource-constrained applications, but it needs to balance the sampling rate and quantization bit-depth for a bit-rate constraint. In this paper, we summarize the commonly used CS quantization frameworks into a unified framework, and a new bit-rate model and a model of the optimal bit-depth are proposed for the unified CS framework. The proposed bit-rate model reveals the relationship between the bit-rate, sampling rate, and bit-depth based on the information entropy of generalized Gaussian distribution. The optimal bit-depth model can predict the optimal bit-depth of CS measurements at a given bit-rate. Then, we propose a general algorithm for choosing sampling rate and bit-depth based on the proposed models. Experimental results show that the proposed algorithm achieves near-optimal rate-distortion performance for the uniform quantization framework and predictive quantization framework in BCS.

Secure Image Authentication Scheme Using Double Random-Phase Encoding and Compressive Sensing

Double random-phase encoding- (DRPE-) based compressive sensing (CS) systems support image authentication for noisy images. When extending such systems to resource-constrained applications, how to ensure the authentication strength for noisy images becomes challenging. To tackle the issue, an efficient and secure image authentication scheme is presented. The phase information of the plain image is generated using DRPE and quantized into a binary image as the authentication information. Meanwhile, a sparser error matrix generated by the same plain image and vector quantization (VQ) image works as the input of CS. The authentication information and VQ indexes are self-hidden into the quantized measurements to construct the combined image. Then, it is permutated and diffused with the chaotic sequences generated from a modified Henon map. After decryption at the receiver side, the verifier can implement the blind authentication between the noisy decoded image and the reconstructed image. Supported by the detailed numerical simulations and theoretical analyses, the DRPE-CSVQ exhibits more powerful compression and authentication capability than its counterpart.