Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization

Abstract

Lightweight cryptography provides security to resource-constrained applications, such as embedded systems and Internet of Things (IoT) devices. This work explores an ultra-lightweight implementation of RC5 block cipher, via two levels of serialization. We also exploit a resource-sharing optimization technique for the data-dependent rotation (DDR) module, since it is the most computationally intensive component of the RC5 block cipher. We present two RC5 hardware structures: (i) an 8-bit serial RC5 architecture using a dual-part DDR unit; this design occupies only 54 slices on a Spartan-6 FPGA device and is 69% superior in terms of Throughput-per-Slice (TPS) compared to the smallest 8-bit AES FPGA implementation, (ii) a novel bit-serial RC5 architecture based on shift-register LUT (SRL) primitives; this design consumes only 20 Spartan-6 slices and shows 81% improvement in throughput performance at the expense of only 5% additional area resources compared to the smallest bit-serial AES design reported. The proposed DDR-based optimizations and efficient time scheduling make our proposed designs outperform most of the state-of-the-art lightweight block cipher designs in terms of hardware efficiency (with regard to TPS).