Resistor Mismatch Research Articles

A −91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping

This article presents a Class-D audio amplifier for capacitive piezoelectric speaker loads. Employing a dual voltage feedback (VFB)/current feedback (CFB) topology, the amplifier is capable of damping LC resonance without using an external damping resistor, therefore reducing system power consumption, cost, and size. Additional power savings are achieved by using a push–pull (PP)-modulated output stage. To mitigate linearity degradation due to the mismatch of the feedback resistors, they are dynamically matched by employing choppers. The prototype, taped out in a BCD 180-nm process, can drive up to 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{F}$ </tex-math></inline-formula> load with a peak current of 4.4 A while achieving an idle power consumption of 122 mW and a peak THD+N of −91 dB.

A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of −109.1 dB and can deliver a maximum of 14 W into an 8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load with 93% efficiency while occupying a silicon area of 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62-<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/&#x2212;1 and 4.78/&#x2212;3.31 LSB, respectively.

On‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications

This study presents a novel hybrid memristor (MR)-complementary metal–oxide–semiconductor-based flash analogue-to-digital converter (ADC). The speed and efficiency of the ADC are important aspects that can significantly affect the overall system performance. The flash ADC is considered the fastest type of ADCs; however, its performance is affected by the resistor mismatch. The proposed flash ADC is the first to use tunable MR to replace conventional resistor to generate accurate reference voltages. This is achieved by utilising the highly analogue behaviour observed in multi-state MR devices fabricated and tested by the authors' group. The electrical parameters of the devices have been extracted by device characterisation, then the voltage-threshold adaptive model (VTEAM) has been used to develop a correlated mathematical and Simulation Program with Integrated Circuit Emphasis (SPICE) device model. The proposed MR-based flash-ADC design solves the issue of resistor mismatch that results in encoding errors by the ability to tune the MR resistance value post-processing. Moreover, being a nanoscale component, the usage of MR significantly improves the area efficiency of the target ADC. Furthermore, the proposed design has improved the ADC transfer function characteristic and has lower differential non-linearity and integral non-linearity errors compared with the conventional design.

A Foreground Self-calibration Technique for High-Resolution Switched-Current R-2R Digital-to-Analog Converters

A foreground calibration technique for switched-current R-2R digital-to-analog converter is proposed. To implement the method, some intermediate nodes are added to the circuit and calibration is done using these nodes to circumvent both current source and resistor mismatches at the output node. A 12-bit, 500-MHz DAC is designed in 0.18 $$\upmu $$m standard CMOS technology with the proposed technique. Simulation results verify that the degraded DAC performance due to the mismatch effects enhances up to 11.5 bits after calibration, imposing a very low power penalty.

A robust calibration method for R-2R ladder-based current-steering DAC

A foreground calibration technique for high-resolution, high-speed R-2R ladder-based current-steering digital-to-analog converter (DAC) is proposed. This kind of converter suffers from both current source mismatch and resistor mismatch. It is proved mathematically that the mismatch effect of the network resistors can be mapped to auxiliary current sources in parallel to the main current sources. Then this current sources can be calibrated in such a way that the output seems to be near ideal. A 125 MHz, 14-bit current-steering DAC is designed in 0.18 μm CMOS with the proposed calibration scheme. Assuming a variance of ±10 Ω for 1kΩ network resistors and ±2% mismatch among current sources, the INL and DNL are improved from 13b and 26b respectively to 0.5b and 0.8b utilizing the calibration. The spurious-free-dynamic-range (SFDR) raises from 63.7 dB to 93.1 dB while SNDR improves from 60.7 dB to 84.2 dB. This occurs for a small power penalty, and this process is resettable for PVT changes.

A New Instrumentation Amplifier Architecture Based on Differential Difference Amplifier for Biological Signal Processing

&lt;p&gt;In this paper, a new Instrumentation Amplifier (IA) architecture for biological signal pro-cessing is proposed. First stage of the proposed IA architecture consists of fully balance differential difference amplifier and three resistors. Its second stage was designed by using differential difference amplifier and two resistors. The second stage has smaller number of resistors than that of conventional one. The IA architectures are simulated and compared by using 1P 2M 0:6-m CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by the proposed IA architecture. Average common-mode gain (Ac) of the proposed IA architecture is 31:26 dB lower than that of conventional one under 3% resistor mismatches condition. Therefore, the Ac of the proposed IA architecture is more insensitive to resistor mismatches and suitable for biological signal processing.&lt;/p&gt;

3-state BTL closed-loop PWM Class D amplifiers

One of the shortcomings of a number of Class D amplifiers (CDAs) designs is their susceptibility to supply noise, quantified by Power Supply Rejection Ratio (PSRR). Reported investigations thereto to-date remain incomplete/over-simplified, particularly the assumption that the AC ground is noise-less and a simplified fully-differential integrator model. In this paper, the effect of supply noise in the AC ground to PSRR is analytically investigated, and the associated analytical expressions derived. Of specific interest, the analysis is applied to the ubiquitous 3-state Bridge-tied-load (BTL) closed-loop PWM CDA, taking into consideration not only the effect of the non-ideal AC ground, but also the effect of the resistor and capacitor mismatch based on a realistic fully-differential integrator model. Further, the PSRR analysis of 3-state BTL closed-loop CDAs has to date been limited to the single-feedback topology and in this paper, extended to the double-feedback topology. These analyses and derived equations herein are useful as they provide valuable insights to CDA designers into the PSRR mechanisms--for example, the counter-intuitive observation that the CDA with 1st-order integrators provides similar or better PSRR than the CDA with 2nd-order integrators if both CDAs are designed to the same carrier attenuation--including the effect of various circuit parameters, and ensuing trade-offs. The derived analytical expressions are verified by means of HSPICE simulations and on the basis of practical measurements on discretely-realized CDAs.

A Wide Linear Output Range Biopotential Amplifier for Physiological Measurement Frontend

This paper presents a wide linear output range biopotential amplifier for physiological measurement frontend. The proposed amplifier consists of an open-loop rail-to-rail differential pair in the first stage and a closed-loop common source amplifier in the second stage, which extends the linear output range by maintaining a constant voltage gain with amplifier output level variation. The nMOS and pMOS gain enhancement switches provide additional compensation for the voltage gain degradation as the amplifier output level moves toward the supply rails. In addition, voltage buffers are used after the first and second stages to alleviate the loading effect. This enables using small-sized feedback resistors, where the amplifier performance is relatively insensitive to resistor mismatch. Aside from the wide linear output range, this approach leads to small silicon area, low power, and relatively high common mode rejection ratio and power supply rejection ratio, which are highly demanding for portable and implantable biomedical instrumentation frontend. The proposed amplifier is implemented using CMOS 0.35μm technology (3.3 V supply) with core area of 0.063 mm2. Measurement results show a stable voltage gain of 46.3 dB for amplifier output range from 0.15 to 3.12 V, and a 0.04% total harmonic distortion with input amplitude of 15 mVpp. Furthermore, the amplifier operation is demonstrated with an actual ECG measurement setup.

Thermal Flow-Sensor Drift Reduction by Thermopile Voltage Cancellation via Power Feedback Control

The research question that is addressed in this paper relates to the performance limitations of thermal flow sensors due to miniaturization. Sensor elements in current microflow sensors are mostly made by metal thin films. The problem is that thin-films reproduce poorly and that practically all material properties are subject to drift. This drift and poor reproducibility translates directly into the accuracy of thermal microflow sensors. This paper presents a thermal flow sensor consisting of freely suspended silicon-rich silicon-nitride microchannels with an integrated thermopile in combination with up and downstream Al heater resistors. The drift-free zero offset of a thermopile at uniform temperature is exploited in a feedback loop controlling the dissipated powers in Al heater resistors, reducing inevitable influences of resistance drift, and mismatch of thin-film metal resistors. The control system attempts to cancel the flow-induced temperature imbalance across the thermopile by controlling a power difference between both heater resistors, thereby giving a measure of the flow rate nearly independent of material drift.

A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability

This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.

Package Stress Monitor to Compensate for the Piezo-Hall Effect in CMOS Hall Sensors

Package-induced stress changes the sensitivity of planar Hall plates via the piezo-Hall effect. In this paper, we present a novel stress sensor that allows us to compensate for this undesired mechanical cross-sensitivity. The new CMOS-compatible sensor is based on a Wheatstone bridge built of eight appropriately arranged n- and p-doped piezoresistors. The differential output signal $V_{\rm bridge}$ of the sensor is proportional to the sum of in-plane normal stresses $\sigma_{xx}+\sigma_{yy}$ with the sensitivity $S_{{\rm bridge},\sigma}=\partial\left(V_{\rm bridge}/V_{\rm bias}\right)/\partial\left(\sigma_{xx}+\sigma_{yy}\right)=-0.047~{\rm GPa}^{-1}$ . Doping concentrations larger than $10^{19}~{\rm cm}^{-3}$ for both the n- and p-type resistors are used to minimize the parasitic resistor mismatch due to the junction field effect. Simultaneously, the highly doped resistors keep the relative thermal cross-sensitivity of the sensor as small as $74~{\rm ppm~K}^{-1}$ . In contrast to conventional sensor rosettes, the new sensor has the advantage of offering a differential output signal. The measured signal is successfully used to decrease the stress-impact on the sensitivity of CMOS Hall sensors by a factor of five.

Nonlinearity analysis of double multi-bit decided folded resistor string digital-to-analog converter

This paper presents a double multi-bit decided folded resistor string digital-to-analog converter that notably reduces the number of output voltage nodes compared with the conventional resistor string digital-to-analog converter. A theoretical nonlinearity analysis of the newly proposed topology based on random, zero-mean, and normally distributed resistor mismatches is also presented. The derived equations enable circuit designers to quickly select the most suitable design for their applications by calculating the required resistor mismatch. Monte-Carlo simulation results show strong agreement with theoretical equations and confirm their accuracy.

Nonlinearity analysis of folded Multi-LSB decided resistor string digital to analog converter

A theoretical nonlinearity analysis of folded multi-LSB decided resistor string DAC is presented. By the derived theoretical equations, circuit designers can calculate the required resistor mismatch very quickly, thus reducing the design time. The Monte-Carlo simulation results agree well with the theoretical equations and confirm their accuracy.

High-level modeling of resistor string based digital-to-analog converters

To obtain a high performance CMOS resistor string digital-to-analog converter (DAC), one of the key design issues is the mismatch in the resistor ratio. This mismatch causes nonlinearity errors such as integral nonlinearity (INL) and differential nonlinearity (DNL), degrading the performances of the converter. Usually these matching properties are taken into account during the design phase by using time consuming and computational intensive transistor-level Monte Carlo simulations for the process technology corner. Recent research aims at reducing the design time by exploiting high-level modeling of converters as a trade-off between simulation time and modelling accuracy. In this work an analytical model for resistor mismatch in DACs is presented and implemented in MATLABTM environment. The model utilizes geometrical size of resistors and statistical data of the technology process. Starting from random process variations on geometries it was possible to estimate DNL and INL with very short time simulations. The proposed model is valid both for single stage resistor string DACs or segmented ones. The model can be used to speed up the design of resistor-string based DACs, or as a starting point to develop more accurate models by taking into account high-order effects. The model was successfully used to design a 10bit resistor string DAC in a 0.18 μm BCD technology with DNL and INL lower than 1 LSB (in absolute value). Since the complexity of the DAC is dominated by the resistor string, its optimization since the early design steps, enabled by the proposed high-level model, allowed to minimize area versus state of the art.

Improvement of Power Supply Rejection Ratio in Wheatstone-bridge based piezoresistive MEMS

This paper deals with the design of MEMS-based sensors with piezoresistive transduction. It is demonstrated that when the sensor topology does not allow a perfect matching of resistances in the conditioning circuit (typically a Wheatstone bridge), the resolution of the system is limited by the ability to reject power supply noise. As this ability increases when the output offset of the bridge decreases, the proposed architecture implements a feedback loop to control MOS transistors inserted in the Wheatstone bridge to compensate resistor mismatches. This zero-offset bridge exhibits a very good offset cancellation and therefore a better resolution.

A digital calibration algorithm for implementing accurate on-chip resistors

A digital calibration algorithm that provides a systematic method for implementing accurate integrated resistors without compromising linearity or noise performance is described. The technique uses a single external resistor as a reference to implement multiple, different valued integrated resistors without requiring any accurate reference voltage. The algorithm provides a method to calibrate several on-chip resistors without replicating the calibration circuit, and it can achieve an arbitrary accuracy limited only by the external resistor's accuracy and mismatch errors. Terminations for two high speed wire line transceivers are implemented using the algorithm and simulations and measurements results show adequate performance across process, temperature, and supply voltage.

Mismatch in diffusion resistors caused by photolithography

During the qualification of a 0.35-/spl mu/m CMOS process, it was observed that diffusion resistors showed a systematic mismatch, depending on the position on the wafer. The mismatch increased from the center of the wafer to the outer regions. Various experiments showed that the mismatch was caused by spinning the wafer during the resist development process. Changing this process eliminated the systematic diffusion resistor mismatch.

Development of a novel thick-film strain gauge sensor system

In this paper a novel strain gauge system on stainless steel and 96% alumina substrates is described incorporating a Wheatstone bridge network, thick-film piezoresistive strain gauges, instrumentation, and a novel thermal and resistor mismatch tolerance correction software. The resistors in the Wheatstone bridge are fabricated with a novel mixture of ruthenium, bismuth and indium oxides and three different thick-film layouts are used. Mechanical measurements are performed using the cantilever beam set-up. The linearity, hysteresis, repeatability, reproducibility, creep, stability and temperature effects are measured for the novel thick-film pastes. The linearity and temperature effect on the output of the different bridge layouts are also examined. The printing of resistors using thick-film technology can result in resistor tolerances of %. Also, thick-film piezoresistors are intrinsically cross sensitive to temperature. These two properties cause an offset voltage to appear at the output of the bridge under no-load/load conditions and a subsequent error in the calculated applied strain. In order to compensate for the offset error voltage, novel correction software has been developed and implemented using a microcontroller. The error in the predicted strain was measured before and after application of the correction software under different bridge layouts and temperature conditions. The error was reduced from a maximum of 45% to approximately 1%. The effectiveness of the correction software in reducing the error suggests that this technique can be used without the need for trimming or bridge balancing.

An accurate reference‐generating circuit for successive approximation current mode A/D converters

AbstractAs pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5 V, current mode signal‐processing techniques will surely become increasingly important and attractive. This paper presents the design of a reference‐generating (RG) circuit which employs a current mode divide‐by‐two circuit. Current dividers are usually implemented by using resistor networks or weighted transistors. the division accuracy of such solutions is limited by resistor or transistor mismatch. In this study the proposed divide‐by‐two circuit does not rely on well‐matched components and high‐gain op amps to achieve high accuracy. This paper also addresses the relationship among the operation and accuracy of the division process, the transistor mismatch and the resolution of a converter which employs the RG circuit. the proposed RG circuit can be implemented not only for medium‐speed successive approximation current mode A/D converters but also for A/D converter arrays achieving a high conversion rate.