A Foreground Self-calibration Technique for High-Resolution Switched-Current R-2R Digital-to-Analog Converters

Abstract

A foreground calibration technique for switched-current R-2R digital-to-analog converter is proposed. To implement the method, some intermediate nodes are added to the circuit and calibration is done using these nodes to circumvent both current source and resistor mismatches at the output node. A 12-bit, 500-MHz DAC is designed in 0.18 $$\upmu $$m standard CMOS technology with the proposed technique. Simulation results verify that the degraded DAC performance due to the mismatch effects enhances up to 11.5 bits after calibration, imposing a very low power penalty.