Abstract
A foreground calibration technique for high-resolution, high-speed R-2R ladder-based current-steering digital-to-analog converter (DAC) is proposed. This kind of converter suffers from both current source mismatch and resistor mismatch. It is proved mathematically that the mismatch effect of the network resistors can be mapped to auxiliary current sources in parallel to the main current sources. Then this current sources can be calibrated in such a way that the output seems to be near ideal. A 125 MHz, 14-bit current-steering DAC is designed in 0.18 μm CMOS with the proposed calibration scheme. Assuming a variance of ±10 Ω for 1kΩ network resistors and ±2% mismatch among current sources, the INL and DNL are improved from 13b and 26b respectively to 0.5b and 0.8b utilizing the calibration. The spurious-free-dynamic-range (SFDR) raises from 63.7 dB to 93.1 dB while SNDR improves from 60.7 dB to 84.2 dB. This occurs for a small power penalty, and this process is resettable for PVT changes.
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