Resistive Random Access Memory Array Research Articles

Suppress variations of analog resistive memory for neuromorphic computing by localizing Vo formation

Reducing device to device variations of filamentary analog resistive random access memory (RRAM) is crucial for neuromorphic computing. Larger variations decrease the computing accuracy of the neuromorphic network. One of the main factors for the variations of filamentary RRAM is the random nature of filament formation. This work presents a defect engineering approach using the atomic layer deposition method to localize the oxygen vacancies (Vo) formation uniformly, which results in uniform multi-weak-filaments formed in RRAM devices. The variation of linearity and dynamic ON/OFF ratio in different devices can be suppressed using the proposed method. Besides the variation control in this work, the retention and read disturbance are also optimized by increasing the Vo migration barrier, which are also important for neuromorphic network. The analog RRAM array is demonstrated with good uniformity of analog switching behavior, fast speed, long retention, small read disturbance, which shows tremendous potential in developing large-scale RRAM based neural networks.

Unveiling the Switching Mechanism of a TaO<italic>x</italic>/HfO2 Self-Selective Cell by Probing the Trap Profiles With RTN Measurements

Self-selectivecells (SSCs) with built-in nonlinearity provide a promising solution for overcoming the leakage current issue of 3-D vertical resistive random access memory arrays. However, deep understanding of the switching mechanism of the SSC device is still lacking, hindering the effective improvement of the device performance. In this letter, we investigated the switching mechanism of the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SSC device by probing the trap profiles with RTN measurements. Both the vertical locations and energy levels (X <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of defects in the HRS and LRS could be calculated by the bias-dependence of the capture and emission time constants (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> and τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ). Using the comparison of the defect profiles before and after the resistive switching, an active region in the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> layer adjacent to the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer could be clearly identified. Based on these results, a clear picture of resistive switching in the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SSC was obtained.

Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays

Resistive random access memory (RRAM) is a promising emerging technology to provide nonvolatile and scalable data storage in advanced technologies. As a noncharge-based device, the intrinsic RRAM device is immune to single-event effects. However, single-event upset (SEU) due to the MOSFET in the one-transistor-one-RRAM (1T1R) array can be observed. A novel methodology, which can be easily integrated to the other memory system components, is proposed in this paper to detect and correct SEU in 1T1R RRAM memory array. Using the HfO x 1T1R RRAM array as an example, our simulation results show that, for an 8-Gb memory array, the proposed technique can detect and fix the soft errors induced by the heavy ion strikes with 0.66% increase in the chip area. Also, the suggested methodology minimally increases the energy consumption of the read and write operations by 0.2% and 0.1%, respectively.

CACF

Emerging Resistive Random Access Memory (ReRAM) is a promising candidate as the replacement for DRAM due to its low standby power, high density, high scalability, and nonvolatility. By employing the unique crossbar structure, ReRAM can be constructed with extremely high density. However, the crossbar ReRAM faces some serious challenges in terms of performance, reliability, and energy consumption. First, ReRAM’s crossbar structure causes an IR drop problem due to wire resistance and sneak currents, which results in nonuniform access latency in ReRAM banks and reduces its reliability. Second, without access transistors in the crossbar structure, write disturbance results in serious data reliability problem. Third, the access latency, reliability, and energy use of ReRAM arrays are significantly influenced by the data patterns involved in a write operation. To overcome the challenges of the crossbar ReRAM, we propose a novel circuit architecture co-optimization framework for improving the performance, reliability, and energy use of ReRAM-based main memory system, called CACF. The proposed CACF consists of three levels, including the circuit level, circuit architecture level, and architecture level. At the circuit level, to reduce the IR drops along bitlines, we propose a double-sided write driver design by applying write drivers along both sides of bitlines and selectively activating the write drivers. At the circuit architecture level, to address the write disturbance with low overheads, we propose a RESET disturbance detection scheme by adding disturbance reference cells and conditionally performing refresh operations. At the architecture level, a region partition with address remapping method is proposed to leverage the nonuniform access latency in ReRAM banks, and two flip schemes are proposed in different regions to optimize the data patterns involved in a write operation. The experimental results show that CACF improves system performance by 26.1%, decreases memory access latency by 22.4%, shortens running time by 20.1%, and reduces energy consumption by 21.6% on average over an aggressive baseline. Meanwhile, CACF significantly improves the reliability of ReRAM-based memory systems.

In Situ TEM Observation of Dynamic Switching Behaviors in Vrram

Resistive random access memory (RRAM) is considered as a promising candidate for the next-generation nonvolatile memories (NVM) due to its high storage density, reduced power consumption, and fast switching speed. Transition metal oxides are widely utilized to RRAM as insulator, which exhibit stable structure, high endurance and retention, and shrinking ability under several nanometers. In order to realize higher endurance and stability while reducing the size, knowing the mechanism of filaments formation and the interaction between adjacent nanodevices are essential. In this work, three-dimensional vertical RRAM (VRRAM) array architectures were built to access and organize data, which are expected to high density application potential. In our simple MIM structure, ZnO is the insulator, and Ag and Pt are served as active electrode and inert electrode, respectively. Each electrodes intersection contains two types of RRAM devices (Ag/ZnO/Pt, Pt/ZnO/Pt). By utilizing in-situ transmission electron microscope (TEM), we could observe the dynamic switching behaviors of two neighboring devices and realize the interaction between them. While the devices sizes scale down to few nanometers scale, the evolution of different types of filaments provides important information to improve the stability and performance of the devices.

Selector-Less Graphite Memristor: Intrinsic Nonlinear Behavior with Gap Design Method for Array Applications

Resistive random access memory (RRAM) using various binary metal oxide structures have attracted attentions since the current nonvolatile memory (NVM) has been approaching the scaling limit. RRAMs has excellent scalability, high speed and low power operation ability which is desired for current hardware needs. Meanwhile, selector devices are essential to suppress the sneak path issue which causes reading errors and hinders the implementation of RRAM in high-density cross-bar array architecture. However, additional selector device as commonly proposed one selector-one resistor (1S-1R) design, rises the process complexity and cost. In this work, selectorless graphite-based memristor devices have been demonstrated by utilizing the nonlinear (NL) resistive switching (RS) characteristics with gap design method for RRAM array applications. The starting substrates are heavily-doped N+ Si wafers, and titanium nitride of 200 nm thickness was deposited on N+ Si substrate as bottom electrode. Then, 5 nm of graphite and 7 nm of HfOx were deposited as RS dielectric layers for bilayer (HfOx/C) structures by RF sputtering method. Pt (165nm) was deposited as top electrodes for RRAM devices (not showed here). Fig. 1 shows bipolar I-V characteristics during DC voltage sweeps for single-layer HfOx and HfOx/C stacked devices. Both SET and RESET voltages are around 1 V/-1 V in single-layer HfOx devices as the bilayer devices possibly owing to inserting a HfOx stack layer, which has higher oxygen concentration and potentially be beneficial for low voltage operating applications. Comparing the bilayer structure to the single-layer HfOx structure, where dI/dV increases indicating that there was significantly increased resistance at low voltage region for sneak path current suppression. The graphite-stacked memristor has been confirmed with the nonlinearity than HfOx single layer structure and was proposed as a solution for sneak path issue in crossbar array applications. Nonlinearity (NL) is defined as the ratio of the current at full read voltage (i.e. -0.6 V) to the current at 1/3 read voltage (-0.2 V). The higher nonlinearity, the better ability is to avoid the sneak current interference. Fig. 2 shows the NL for graphite-stacked RRAM with varied graphite thickness i.e. 0, 3, 5, 8, 10 nm (30 DC cycles). The NL is increasing with the portions of graphite thickness in the bilayer stacks. The single layer and bilayer devices with narrow SET/RESET voltage variation and have been found to exhibit low operating voltage (~1 V), which are independent on the graphite thickness in the bilayer structures (Fig. 3). Fig.4 shows the HRS and LRS of all graphite memristors as compared to HfOx layer device. The memory window i.e. ratio of ILRS /IHRS enlarges in the graphite memristors, which is suggested to the graphite oxide (GO) formation caused HRS current reduction. The NL characteristics in ILRS of all the devices under different SET compliance current limits (CCL) as showed in Fig. 5. With a thin graphite layer (5 nm) on the bottom of HfOx (7 nm) layer, the NL is ~3x of the single-layer HfOx layer devices. This makes graphite-stacked bilayer devices a potential candidate for 1R selectorless RRAMs. The NL of graphite-stacked RRAM can be optimized by adjusting SET CCL, as called “gap design method” for memristors. To eliminate device-to-device (D2D) variation in RRAM, three graphite-stacked memristors in distanced region have been demonstrated with the gap migration with increasing the SET CCL. Also, the RESET current is critical for overall switching power in RRAM applications, is ~1 mA and has been found to be independent of the thickness ratio of stacks (not showed here). Fig. 6 as the schematic of single layer and graphite-stacked structures shows the graphite memristor is the candidate of selectorless RRRAM since the formation of GO as the low-k material in gap modulation. The graphite layer has been confirmed by the XRD pattern in graphite (400) phase direction with resistivity of 0.2643kΩ as the switching layer in stacks, not as the electrode. In this study, build-in NL characteristics have been realized for the graphite selectorless memristors without an diode/selector. The graphite-based memristor are promising for high-density, low-power, selectorless RRAM array applications. The formation of GO with low dielectric constant of 4.3 is beneficial for high NL. The highly NL characteristics observed in graphite-based bilayer devices are desirable in suppressing sneak-path currents in crossbar arrays. Figure 1

An Automated Test Equipment for Characterization of Emerging MRAM and RRAM Arrays

In this paper it is presented a test equipment for the characterization of two different emerging memory technologies like the Thermally Assisted Switching-Magnetic Random Access Memory (TAS-MRAM) and the Resistive Random Access Memory (RRAM). The instrument is developed to allow a fast characterization of test array structures and can be potentially adapted for any other non-volatile memory generation. The hardware architecture is based on a PCI S5933 chipset being the local bus interface of a x86-PC that communicates with the units of the system like 14 bits/100 MHz arbitrary waveform generators and 12 bits/70 MHz programmable measurement units. A user-friendly software interface developed in LabVIEW has been implemented to allow large flexibility in changing the test parameters and a fast analysis of the test results. The instrument performance has been evaluated performing the typical non-volatile memory tests such as endurance and disturbs characterizations, running test flows up to 320 hours for MRAM devices and up to 6,137 hours for RRAM devices.

An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 × 28 image and 10 kernels with a size of 3 × 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO2/Al2O3/TiOx (HAT) RRAM

AbstractComplementary resistive switching (CRS) is a suitable approach to minimize the sneak leakage paths through a large resistive random access memory (RRAM) array. Here, an effective CRS design with a HfO2/Al2O3/TiOx (HAT) trilayer structure integrated in a 3D vertically stacked RRAM array is reported. The design shows voltage‐controlled resistive switching and CRS performance with multilevel operations. High‐speed switching is observed with the HAT design. The device shows SET and the RESET transitions with speeds of −3.5 V@30 ns and +3.8 V@150 ns, respectively. As well as with the DC measurements, the CRS switching is achieved under AC switching dynamics measurement. Maintaining the same applied pulse polarity, the lower amplitude can switch the device to the SET and the higher amplitude can switch it to the RESET. A highly nonlinear (nonlinearity &gt;102) CRS is obtained at a high temperature of 150 °C. In the HAT devices, the origin of CRS is due to the anionic redistribution in HfO2 and TiOx layers, leaving Al2O3 as tunnel barrier. The achievements reported here indicate the applicability of the HAT design for future high‐speed high‐density applications.

Novel Computing Method for Short Programming Time and Low Energy Consumption in HfO2 Based RRAM Arrays

This paper proposes a novel technique for reducing programming time and energy consumption in resistive random access memory (RRAM) arrays based on ramped voltage stress (RVS). RVS method is correlated to conventional constant voltage stress method (CVS) using an analytical model validating RVS as a reliable technique for switching time characterization in RRAM arrays. RVS method is optimized to reduce programming time and energy consumption providing a quantitative and qualitative link between programming method and tails improvement in memory arrays. Switching time distribution is much more controlled: half a decade using optimized RVS in comparison with ~3 decades distribution using conventional CVS method. Energy consumption is reduced by 4 orders of magnitude at $+5\sigma $ quantiles using our proposed technique compared to CVS.

Graphite-based selectorless RRAM: improvable intrinsic nonlinearity for array applications.

Selectorless graphite-based resistive random-access memory (RRAM) has been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without an additional selector or transistor for low-power RRAM array application. The low effective dielectric constant value (k) layer of graphite or graphite oxide is utilized, which is beneficial in suppressing sneak-path currents in the crossbar RRAM array. The tail-bits with low nonlinearity can be manipulated by the positive voltage pulse, which in turn can alleviate variability and reliability issues. Our results provide additional insights for built-in nonlinearity in 1R-only selectorless RRAMs, which are applicable to the low-power memory array, ultrahigh density storage, and in-memory neuromorphic computational configurations.

Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ), and the array bias scheme is a key knob. Lowering array V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance.

Design of Ternary Neural Network With 3-D Vertical RRAM Array

Recently, 2-D cross-point array of resistive random access memory (RRAM) has been proposed for implementing the weighted sum and weight update operations to accelerate the neuro-inspired learning algorithms on chip. This paper aims to extend such 2-D cross-point array to 3-D vertical array for storing and computing the large-scale weight matrices in the neural network. Considering the fabrication and 3-D integration of analog synapses (i.e., multilevel RRAM devices) are premature at this stage, we propose using today’s available digital or binary RRAM devices for implementing a ternary neural network, which aggressively reduces the weight precision to ternary levels (+1, 0,−1) for the weighted sum in both feedforward and backward inference, while the multiple 3-D layers could serve for accumulating the small errors in a higher precision format for weight update. Compared to the 2-D implementation, the proposed 3-D vertical implementation shows larger read/write margin for weighted sum/weight update, smaller latency, and energy consumption for weight update. This paper demonstrates the attractiveness for building a monolithic 3-D neuromorphic hardware platform.

Flexible resistive random access memory devices by using NiOx/GaN microdisk arrays fabricated on graphene films

We report flexible resistive random access memory (ReRAM) arrays fabricated by using NiOx/GaN microdisk arrays on graphene films. The ReRAM device was created from discrete GaN microdisk arrays grown on graphene films produced by chemical vapor deposition, followed by deposition of NiOx thin layers and Au metal contacts. The microdisk ReRAM arrays were transferred to flexible plastic substrates by a simple lift-off technique. The electrical and memory characteristics of the ReRAM devices were investigated under bending conditions. Resistive switching characteristics, including cumulative probability, endurance, and retention, were measured. After 1000 bending repetitions, no significant change in the device characteristics was observed. The flexible ReRAM devices, constructed by using only inorganic materials, operated reliably at temperatures as high as 180 °C.

Mechanism of the Key Impact of Residual Carbon Content on the Reliability of Integrated Resistive Random Access Memory Arrays

Resistive random access memories (RRAM) require high density, low power consumption and high reliability. Systematic statistic electrical, material and theoretical studies were demonstrated in this work to point out and clarify a key impact of carbon residues on the resistive switching (RS), particularly the endurance, of the integrated HfO2-based 4 kbit RRAM array. The mechanism of the carbon atoms interacting with oxygen vacancies and serving also as filament was understood in nanoscale by performing density functional theory (DFT) calculations. Under an oxygen-deficient environment, carbon atoms tend to fill in oxygen vacancy (VO··) sites and could form conductive filaments which require higher energy to be broken compared to the original VO·· filaments. By controlling the residual carbon concentration lower than 4%, highly reliable HfO2-based integrated 4 kbit RRAM array was achieved, which is of great interest for future nonvolatile memories.

A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array

The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 μA due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design.

Demonstration of Logic Operations in High-Performance RRAM Crossbar Array Fabricated by Atomic Layer Deposition Technique

In this paper, resistive random access memory (RRAM)-based crossbar arrays with the cell structure of Pt/[AlOy/HfOx]m/TiN were fabricated by using atomic layer deposition (ALD) technique. The RRAM devices in the arrays show excellent performances such as good uniformity and high reliability. Based on the fabricated RRAM array, a complete set of basic logic operations including NOR and XNOR were successfully demonstrated.

Highly Non-linear and Reliable Amorphous Silicon Based Back-to-Back Schottky Diode as Selector Device for Large Scale RRAM Arrays

In this work, we present silicon process compatible, stable and reliable (>108 cycles), high non-linearity ratio at a half-read voltage (>5 × 105), high speed (<60 ns), and low operating voltage (<3V) back-to-back Schottky diodes. Materials choice of electrode, the thickness of semiconductor layer and doping level are investigated by numerical simulation, experiments and current-voltage equations to give a general design consideration when back-to-back Schottky diodes are used as selector device for Resistive Random Access Memory (RRAM) arrays.

Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO2-based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing

Resistive random-access memory (ReRAM) is regarded as one of the most promising alternative nonvolatile memory technologies for its advantages in very-high-storage density, simple structure, low power consumption, and long endurance, as well as good compatibility with traditional complimentary metal-oxide-semiconductor (CMOS) technology. In addition to the data storage, ReRAM can also be used for logic operation and computation, demonstrating a great potential in developing a non-von Neumann computing system. Extensive studies on ReRAM technology, including material, device process, cell and array structure, circuit, and architecture, have been conducted in recent years. In this article, we provide a broad perspective on ReRAM technology for future storage and computing. The models, challenges, and applications are also summarized.