Resistive Random Access Memory Array Research Articles

Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System

Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1.

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

A Plasmonic Optoelectronic Resistive Random-Access Memory for In-Sensor Color Image Cryptography.

The optoelectronic resistive random-access memory (RRAM) with the integrated function of perception, storage and intrinsic randomness displays promising applications in the hardware level in-sensor image cryptography. In this work, 2D hexagonal boron nitride based optoelectronic RRAM is fabricated with semitransparent noble metal (Ag or Au) as top electrodes, which can simultaneous capture color image and generate physically unclonable function (PUF) key for in-sensor color image cryptography. Surface plasmons of noble metals enable the strong light absorption to realize an efficient modulation of filament growth at nanoscale. Resistive switching curves show that the optical stimuli can impede the filament aggregation and promote the filament annihilation, which originates from photothermal effects and photogenerated hot electrons in localized surface plasmon resonance of noble metals. By selecting noble metals, the optoelectronic RRAM array can respond to distinct wavelengthsand mimic the biological dichromatic cone cells to perform the color perception. Due to the intrinsic and high-quality randomness, the optoelectronic RRAM can produce a PUF key in every exposure cycle, which can be applied in the reconfigurable cryptography. The findings demonstrate an effective strategy to build optoelectronic RRAM for in-sensor color image cryptography applications.

Investigation on self-rectifying properties of Pt/HfO2/Ti with rivet-like structure based on ALD conformal technology

This work explores an architecture for nonvolatile resistive random-access memory (RRAM) systems. The study proposes a self-rectifying RRAM device utilizing a two-terminal 1R selector that harmonizes the gate control efficacy of transistors with the inherent simplicity of diode structures. A rivet-like HfO2-based RRAM array is meticulously constructed through atomic layer deposition (ALD), aiming to enhance device performance and retention stability. The conformal fabrication technique of ALD method is critical in achieving uniform coverage of isolation layers and precise electrode placement, which is instrumental in the fabrication of high-performance memory cells. Empirical analyses indicate significant improvements in rectification and ON/OFF ratios compared to existing RRAM models, bolstered by compatibility with established CMOS processes. It reveals that these advances are conducive to scalable, high-density memory integration, positioning the RRAM as a viable contender for future computational applications that require high efficiency and neuromorphic computing capabilities.

The study of lithographic variation in resistive random access memory

Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (~30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4×, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

Insulator Metal Transition-Based Selector in Crossbar Memory Arrays

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM’s competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors.

Demonstration of transfer learning using 14 nm technology analog ReRAM array

Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of co-optimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

A novel read circuit for RRAM based on RC delay effect

AbstractIn this paper, a novel Resistive Random‐Access Memory (RRAM) read circuit has been designed and verified by simulation based on the RRAM model and parasitic capacitance of the circuit. Simulation results demonstrate the feasibility and effectiveness of the proposed circuit, with accurate reading of RRAM states and fast reading speed in the nanosecond range. The sense margin of the proposed circuit has improved as the array size increases, enhancing its application for advanced node RRAM array manufacture. Compared with conventional circuits, the proposed circuit achieved power consumption reduction of 6% and area reduction of 46.9 um2, resulting in a 97.5% reduction in area, providing an effective solution to address the cost and chip size challenges associated with RRAM industrialization.

A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array.

Enhancing the ubiquitous sensors and connected devices with computational abilities to realize visions of the Internet of Things (IoT) requires the development of robust, compact, and low-power deep neural network accelerators. Analog in-memory matrix-matrix multiplications enabled by emerging memories can significantly reduce the accelerator energy budget while resulting in compact accelerators. In this article, we design a hardware-aware deep neural network (DNN) accelerator that combines a planar-staircase resistive random access memory (RRAM) array with a variation-tolerant in-memory compute methodology to enhance the peak power efficiency by 5.64× and area efficiency by 4.7× over state-of-the-art DNN accelerators. Pulse application at the bottom electrodes of the staircase array generates a concurrent input shift, which eliminates the input unfolding, and regeneration required for convolution execution within typical crossbar arrays. Our in-memory compute method operates in charge domain and facilitates high-accuracy floating-point computations with low RRAM states, device requirement. This work provides a path toward fast hardware accelerators that use low power and low area.

A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing

Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in high-throughput and high-resolution cases. This paper proposes an analog-oriented RRAM array/read circuits co-design technique to solve the trade-offs between distortion, power consumption, throughput, and chip area. In previous works, the RRAM array is built in a digital mindset that access transistors only serve as switches. Instead, this work investigates a new perspective that utilizes access transistors as common-gate current buffers which reduce the operating current and amplify the output impedance. To further decrease the complexity of peripheral circuits, the idea of In-ADC Computing (IAC) is proposed, which performs shift-add operation together with analog-to-digital conversion. Benefiting from proposed ideas, a pre-trained VGG-8 network based on the CIFAR-10 dataset can be implemented and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit MAC operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still be able to operate in a power-efficient way.

Analysis of VMM computation strategies to implement BNN applications on RRAM arrays

The growing interest in edge-AI solutions and advances in the field of quantized neural networks have led to hardware efficient binary neural networks (BNNs). Extreme BNNs utilize only binary weights and activations, making them more memory efficient. Such networks can be realized using exclusive-NOR (XNOR) gates and popcount circuits. The analog in-memory realization of BNNs utilizing emerging non-volatile memory devices has been widely explored recently. However, most realizations typically use 2T-2R synapses, resulting in sub-optimal area utilization. In this study, we investigate alternate computation mapping strategies to realize BNN using selectorless resistive random access memory arrays. A new differential computation scheme that shows a comparable performance with the well-established XNOR computation strategy is proposed. Through extensive experimental characterization, BNN implementation using a non-filamentary bipolar oxide-based random access memory device-based crossbar is demonstrated for two datasets: (i) experimental characterization was performed on a thermal-image based Rock-Paper-Scissors dataset to analyze the impact of sneak-paths with real-hardware experiments. (ii) Large-scale BNN simulations on the Fashion-MNIST dataset with multi-level cell characteristics of non-filamentary devices are performed to demonstrate the impact of device non-idealities.

Quantization Design for Resistive Memories With Multiple Reads

Due to the crossbar array architecture, the sneakpath problem severely degrades the data integrity in the resistive random access memory (ReRAM). In this letter, we investigate the channel quantizer design for ReRAM arrays with multiple reads, which is a typical technique to improve the data recovery performance of data storage systems. Starting with a quantized channel model of ReRAM with multiple reads, we first derive a general approach for designing the channel quantizer, for both single-bit and multiple-bit quantizations. We then focus on the single-bit quantization, which is highly suitable for practical applications of ReRAM. In particular, we propose a semi-analytical approach to design the multiple-read single-bit quantizer with less complexity. We also derive the theoretical bit-error probability of the optimal single-bit detector/quantization as the benchmark. Results indicate that the multiple-read operation is effective in improving the error rate performance of ReRAM. Moreover, our proposed multiple-read detector outperforms the prior art detector and achieves the performance of the optimal detector.

Analysis of the Electrical ReRAM Device Degradation Induced by Thermal Cross‐Talk

AbstractA switching of resistive memory cells leads to a local accumulation of Joules heat in the device. In resistive RAM (ReRAM) arrays, the heat generated in one cell spreads via common electrode metal lines to the neighboring cells and may cause their performance degradation. The performance degradation results in reduced number of switching cycles and, in extreme cases, even in a loss of a bit, caused by the rupture of the nanofilament. The authors propose a thermal analysis of the thermal cross‐talk, describe its impact on cells’ electric performance, and identify three major mechanisms for the ReRAM reliability: (i) thermal conductivity, (ii) the specific heat capacity, and (iii) geometry of the electrodes. Several ReRAM arrays are manufactured to vary thermal conductivity, specific heat and geometry of the electrodes by depositing eight different inert electrodes: Pt(50 nm)/Ti(30 nm), Ru(50 nm)/Ti(30 nm), Co(50 nm)/Ti(30 nm), Pt(50 nm/Cu(100 nm)/Ti(30 nm), Pt(50 nm)/ Cu(200 nm)/Ti(30 nm), Ru(50 nm/Cr(30 nm), Ru(50 nm)/Ti(50 nm), and Rh(50 nm)/Cr(30 nm). The experimentally found differences of the degradation of electric performance of the array cells performed under identical circumstances can be correctly predicted by the proposed thermal analysis using the material properties and geometry parameters of the electrodes.

Fully Binarized, Parallel, RRAM-Based Computing Primitive for In-Memory Similarity Search

In this brief, we propose a fully-binarized XOR-based IMSS (In-Memory Similarity Search) using RRAM (Resistive Random Access Memory) arrays. XOR (Exclusive OR) operation is realized using 2T-2R bitcells arranged along the column in an array. This enables simultaneous match operation across multiple stored data vectors by performing analog column-wise XOR operation and summation to compute HD (Hamming Distance). The proposed scheme is experimentally validated on fabricated RRAM arrays. Full-system validation is performed through SPICE simulations using open source Skywater 130 nm CMOS PDK demonstrating energy of 17 fJ per XOR operation using the proposed bitcell with a full-system power dissipation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$145~\mu \text{W}$ </tex-math></inline-formula> . Using projected estimations at advanced nodes (28 nm) energy savings of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 1.5\times $ </tex-math></inline-formula> compared to the state-of-the-art can be observed for a fixed workload. Application-level validation is performed on HSI (Hyper-Spectral Image) pixel classification task using the Salinas dataset demonstrating an accuracy of 91%.

A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory

Resistive random access memory (RRAM) is a promising emerging nonvolatile memory (NVM) due to its large resistance ratio in different switching states. To improve memory density and reduce cost-per-bit, multi-level cell (MLC) RRAM stores multiple bits in a single cell, compared to a single-level cell (SLC). However, random mismatch, process variation, and resistance shift lead to reliability issues, degrade the probability of correct read, and increase the bit error rate (BER). This paper presents a time-based sensing scheme for robust read operation and extends to multi-level sensing for SLC and MLC RRAM arrays. Bit line (BL) voltage is converted into time delay by a voltage-to-time converter (VTC) and compared with the implicit timing reference generated by a delay line. By detecting different states in the time domain, the proposed time-mode sense amplifier (TSA) requires no analog reference voltage or current, which is used in the conventional voltage-mode sense amplifiers (VSA) or current-mode sense amplifiers (CSA). Power gating is employed to enable the time sampling only at the sensing points to suppress the short-circuit current. A charge sharing-induced error compensation (CSEC) circuit is used to eliminate the charge sharing-induced voltage drop and expand the sense margin by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.56\times $ </tex-math></inline-formula> . Monte Carlo simulations in 40nm technology show that the proposed TSA improves read reliability and reduces BER by 3–4 orders of magnitude compared to conventional VSA and CSA. The proposed time-based sensing scheme operates from 0.7-1.2 V supply and consumes 49 fJ/bit for read operation under a nominal 1.2 V supply.

Enhanced Current-voltage Nonlinearity by Controlling Oxygen Concentration of TiO&lt;SUB&gt;x&lt;/SUB&gt; Buffer Layer for RRAM Passive Crossbar Array

As a next-generation memory, resistive random access memory (RRAM) is attracting attention for its fast speed and non-volatility. Nevertheless, an additional selecting element is required to solve the sneak path problem. However, nonlinear devices such as transistors and selectors not only degrade density of the RRAM array, but also increase difficulty of 3D integration. Therefore, in this study, we propose a method for improving the current-voltage (I-V) nonlinearity of an Pt/Al₂O₃/TiOSUBx/SUB/Ti/Pt RRAM. Oxygen concentration was controlled based on electrical flexibility of TiOSUBx/SUB encompassing metallic and semiconducting properties; and three devices with different TiOSUBx/SUB were fabricated. As the O/Ti atomic ratio increases from 1.31 to 1.74, the enhanced I-V nonlinearity was confirmed, which was also quantitatively verified through fitting with a hyperbolic sine function. Reflecting the measured nonlinearity, RRAM passive array was constructed and its read margin was investigated by SPICE simulation. As a result, it is demonstrated that the read margin was improved by increasing the nonlinearity. For TiOSUB1.74/SUB sample which exhibits the highest nonlinearity, a read margin of 22.97% was achieved in 2SUP7/SUP × 2SUP7/SUP array size. By increasing the nonlinearity of RRAM devices, it is expected that RRAM passive array can be utilized for future high-density storage class memory.

Tantalum pentoxide (Ta2O5 and Ta2O5-x)-based memristor for photonic in-memory computing application

Photonic in-memory computing exhibits promising potential to address the inherent limitations of traditional von Neumann architecture. In this study, we demonstrate a tantalum pentoxide (Ta2O5 and Ta2O5−x)-based memristor as a non-volatile memory for photonic in-memory computing functions. The active layer of the memristor on a heavily doped N-Si substrate comprises two films of Ta2O5 and Ta2O5−x with a size of 3 × 3 µm2 of which roughness root-mean-square values are 1.25 nm and 1.59 nm, respectively. A controllable electrical behavior transition from write-once-read-many-times (WORM) memory to resistive random-access memory (RRAM) is achieved by changing the depositional sequence. Benefitting from the visible light response, the in situ photonic Boolean logic operations (“AND/OR”) are achieved in the RRAM device by mixing the light and electric signals, and the power consumption of an “AND” or “OR” operation consumes 4.503 nJ and 4.526 nJ, respectively, proving the superior photonic in-memory computing potential. The basic logic “IMPLICATION” operation is implemented by performing electrical regulation in a circuit with two RRAM devices connected in parallel. Finally, a 5 × 5 RRAM array is developed and thereafter, the array-level logic for image processing applications is realized. The proposed tantalum pentoxide-based memristors possess great potential in constructing efficient in-memory computing architectures.

RM-NTT: An RRAM-Based Compute-in-Memory Number Theoretic Transform Accelerator

As more cloud computing resources are used for machine learning training and inference processes, privacy-preserving techniques that protect data from revealing at the cloud platforms attract increasing interest. Homomorphic encryption (HE) is one of the most promising techniques that enable privacy-preserving machine learning because HE allows data to be evaluated under encrypted forms. However, deep neural network (DNN) implementations using HE are orders of magnitude slower than plaintext implementations. The use of very long polynomials and associated number theoretic transform (NTT) operations for polynomial multiplications is the main bottlenecks of HE implementation for practical uses. This article introduces RRAM number theoretic transform (RM-NTT): a resistive random access memory (RRAM)-based compute-in-memory (CIM) system to accelerate NTT and inverse NTT (INTT) operations. Instead of running fast Fourier transform (FFT)-like algorithms, RM-NTT uses a vector-matrix multiplication (VMM) approach to achieve maximal parallelism during NTT and INTT operations. To improve the efficiency, RM-NTT stores modified forms of the twiddle factors in the RRAM arrays to process NTT/INTT in the same RRAM array and employs a Montgomery reduction algorithm to convert the VMM results. The proposed optimization methods allow RM-NTT to significantly reduce NTT operation latency compared with other NTT accelerators, including both CIM and non-CIM-based designs. The effects of different RM-NTT design parameters and device nonidealities are also discussed.

High-density analog image storage in an analog-valued non-volatile memory array

Data stored in the cloud or on mobile devices reside in physical memory systems with finite sizes. Today, huge amounts of analog data, e.g. images and videos, are first digitalized and then compression algorithms (e.g. the JPEG standard) are employed to minimize the amount of physical storage required. Emerging non-volatile-memory technologies (e.g. phase change memory (PCM), resistive RAM (RRAM)) provide the possibility to store the analog information in a compressed format directly into analog memory systems. Here, we demonstrate with hardware experiments an image storage and compression scheme (joint source-channel coding) with analog-valued PCM and RRAM arrays. This scheme stores information in a distributed fashion and shows resilience to the PCM and RRAM device technology non-idealities, including defective cells, device variability, resistance drift, and relaxation.