Resistive Open Defects Research Articles

Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

A promising new alternative to efficiently solve the Von Neumann bottleneck problem is to adopt In-Memory Computing (IMC) architectures. Beyond the arithmetic operations, IMC architectures aim at integrating additional logic operators directly in the memory array or/and at the periphery in order to provide close computing abilities. However, they are subject to manufacturing defects in the same way as conventional memories. In this paper, a comprehensive model of a 128 × 128 bitcell array based on 28 nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive defects (open and short) injected in the read port. A hierarchical analysis allowing a thorough study of each defect has been carried in order to identify their impact in both memory and computing modes, locally on the defective bitcell as well as globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-short and resistive-open defects.

Identifying Resistive Open Defects in Embedded Cells under Variations

Small Delay Faults (SDFs) due to weak defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is within the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its observability is restricted. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defective devices without a major impact on yield.

On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory

Rapid advancement in deep submicron technology has resulted in the highest occupancy of memory on system-on-chip. The impact of process variations has increased with advanced technology in scaled devices. The reliability of the system majorly depends on embedded memory in the system. But the testing of recent Static Random Access Memory (SRAM) has become significantly difficult with advanced device scaling technology. The unavoidable flaws during fabrication and also the effect of process variations lead to resistive open defects in SRAM cells that change the cell behavior as well as impacts the capability of the fault detection scheme implemented on the system. The detection of weak resistive defects is becoming difficult in advanced technology memory devices. For reliable operation of the system, effective testing technology needs to be implemented for maximum coverage of defects in memory. This work proposes built-in circuitry integrated with SRAM to increase the resistive defect coverage and reduces separate testing circuit requirements. This paper evaluates the effectiveness of the proposed resistive defect detection technique, which uses a predischarged bit line with variable word line stress. Analysis of resistive defect detection by the proposed method is performed on a wide range of resistive open defects introduced at random locations in the memory, with the effects of parasitic components are also investigated for the detection of weak resistive defects. The proposed method implemented on 1 KB of memory provides a minimum area overhead of 3.87 % and the least penalty of 20.48 μs.

Fault Coexistence and Grading Aware TSV Test based on Delay Feature

Screening out the defects in the TSV manufacturing process and eliminating the resistive open fault and leakage fault as early as possible are beneficial to improve the yield and reliability of 3D ICs. The existing prebond test methods are confined to the test accuracy and de- tection range, especially the test confusion prob- lem and the lack of diagnosable ability under the coexistence of multiple faults. Based on the uc- tuation of delay feature caused by faults, a kind of fault coexistence and grading aware TSV test method is proposed to enhance the yield and reli- ability of TSVs in this paper. The reference TSV and the TSV under test are input with test stim- uli simultaneously. Furthermore, the designed delay extraction circuit is utilized to generate the rising edge and the falling edge separately and additional fault grading circuit can be enriched according to the test requirements. Finally, a one bit comparator at the capture end is used to detect whether two pulse signals arrive simul- taneously, so as to determine whether there is a fault and the type of fault. The simulation results indicate that the detection range of resistive open fault is more than 281 , and the detection range of leakage fault is less than 223 M , which is bet- ter than most existing methods. While effective- ly solving resistive open fault and leakage fault, it can also successfully deal with the coexistence of two kinds of faults and achieve a 5-level fault grading ability with relatively low area overhead.

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

The efforts in the semiconductor industry lead to the up-gradation of device size and performance of the devices. Extensive use of cache memory with significant size has become the requirement of most devices, applications, and gadgets. Advanced nanotechnology has resulted in scaled devices and more components with complex circuitry on system-on-chip. The memories are placed incredibly more profound in the die, and memory pins are not accessible readily, leading to more complications in testing the memories. The manufacturing of scaled devices is also a challenging task. A slight variation in doping concentration or process, supply voltage, temperature variations leads to faults in the memory. Advanced technology has increased the possibilities of occurrences of resistive defects in memories. For the smooth operation of systems with high reliability, it is essential to detect all the defects in the memory. In this paper, the detection of resistive defects is proposed at an early stage to increase the life span of the memory cells. Feeble cell detected at an early stage inhibits the more mutilation of the cells and improves memory reliability. An extensive range of defective values is used to analyze the proposed method to cover all positions of the defects in the cell. The proposed method detects the resistive defects with a minimum test time of 81.95μs for 4KB of the memory and contributes a negligible area overhead of 0.77%.

A TSV Test Method for Resistive Open Fault and Leakage Fault Coexisting

Large-size TSVs have larger parasitic capacitance, which leads to more resolution challenges. At the same time, due to the opposite fault effect of resistive open fault and leakage fault in the ring oscillator, the coexistence of two types of faults will cause serious test confusion. These problems significantly increase the difficulty in the TSV test. In this paper, a test method using Schmitt trigger as a TSV receiver is presented to enhance test resolution and reduce test confusion when two kinds of faults exist simultaneously. Schmitt trigger that is characterized by two threshold voltages is used to improve the test resolution. By reducing the supply voltage and checking whether the ring oscillator oscillates, we can identify whether there are two kinds of faults coexisting. HSPICE simulation results based on 45nm CMOS technology demonstrate that the proposed method offers better test resolution in terms of large-size TSVs compared with the existing similar methods, and can distinguish the misdiagnosis when there are two kinds of faults existing simultaneously in a TSV.

New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAMs

This paper presents a complete analysis of the ability of March tests to detect ADOFs (Address Decoder Open Faults) and resistive-ADOFs in address decoders of embedded-SRAMs. Such faults are the primary target of this study because they are notoriously hard-to-detect. With this study, we show that standard March tests without modifications are not able to detect them and we propose to translate the algorithm presented in [1, 2] into March elements. These new March elements involve a particular address sequence and data to be written. For this purpose, we have exploited some Degrees of Freedom of the March tests (DOF I and IV) in order to generate these new March elements for ADOFs detection. Compared to the previous March solutions, these new March elements ensure the fault observation.

Design of Low Power 6T Sram with and without ROFs

An aggressive scaling in size and the increasing number of the transistor count are the important challenge of the design of Integrated Circuit (IC). In the same manner interconnection lines and resistive opens also became a major problem in present nanometer technology. The resistive open faults [ROFs] represent degradation [1] in connectivity’s within a circuit’s interconnections because of unavoidable manufacturing failures present in both current and future developing technologies. The resistive open fault [ROF] is an imperfect circuit connection that can be modelled as a defect resistors between two nodes of the circuit. The Resistive open faults [2] not causes the functionality of the circuit instantly. But, it causes the delay faults. In this research proposal, the impact of resistive open faults measured in 6-Transistors (6T) Static RAM memory cell design. The proposed 6T Static RAM memory cell implemented in 45nm technology by using Cadence Virtuoso library. The main goal of this proposed research work is to analise the effect of resistive open faults and how it reduce delay and power of 6T Static RAM cell. The resultant outputs of proposed 6T SRAM cell operation with and without ROFs will be compared.

Postbond Test of Through-Silicon Vias With Resistive Open Defects

Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 $\text{k}\Omega $ . Experimental work on a 65-nm IC also corroborates the detection capability of the proposal.

Impact of Resistive Open Faults on Inverter Chain and 7t Sram

An aggressive scaling of the technology and the increasing the number of the transistor counts are the major challenge of the design of the Integrated Circuit (IC). As well as interconnection lines and resistive opens have become a problem in modern nanometre technologies. The resistive open faults denote degradation in the connectivity within a circuit’s interconnects because of unavoidable manufacturing failures in both current and developing technologies. The resistive open fault is an imperfect circuit connection that can be modelled as a defect resistor between two circuit nodes. The Resistive open faults will not cause function fault immediately. But, it will cause the delay fault and cannot employ the design of voltage to survey. In this research, find the impact of resistive open fault in the 7-Transistor (7T) SRAM cell design and inverter chain. The proposed 7T SRAM cell design and inverter chain is implemented in 45nm technology with cadence library. The main objective of this proposed research work is to efficiently detect impact of resistive open faults and reduces delay and static and dynamic power of 7T SRAM cell design and inverter chain.

Learning-based reliability assessment method for detection of permanent faults in clockless circuits

Permanent faults are a common issue of contemporary CMOS circuits during fabrication and its lifetime. In order to detect these faults, designers adopt logic and delay-oriented testing approaches to validate the circuit's structure. However, for clockless (i.e. asynchronous) circuits, applying well-known testing approaches is not trivial and bring undesirable overheads. To overcome that, the proposed method in this paper leverages the current signature properties of asynchronous circuits to detect permanent resistive-based faults. Through simulation experiments, we show the natural ability of asynchronous circuits in providing useful current signatures for identifying the presence of resistive-based faults. Moreover, the results demonstrate that our testing technique requires no extra circuitry or power ports to detect resistive-short faults ≤ 3kΩ and resistive-open faults ≥ 70kΩ.

A low-cost concurrent TSV test architecture with lossless test output compression scheme.

As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which are caused by the thermal stress during the fabrication process. These latent defects lead to the deterioration of the electrical performance of TSVs caused by an undesired increase in the resistance-capacitance (RC) delay. For this reason, various post-bond test methodologies have been studied to improve the reliability of 3D-ICs. Cost reduction in these TSV test architectures is also currently being studied by decreasing various factors such as hardware overhead, test time, and the peak current consumption. Usually, a single test-clock-period is required to determine whether the test result contains the defective TSV. When the test result of any TSVs fails, we use another single test-clock-period to classify its defect type. In this paper, we propose a new TSV test architecture to transfer the combined test output of the test result and the specific defect type to the pad during the single test-clock-period. Our proposed test architecture also provides a reliable block-based concurrent testing to optimize the test time by dividing the die into concurrent blocks. The experimental results showed that our proposed test architecture could reduce the test time and the hardware overhead substantially by ensuring that the reasonable peak power consumption for mass production was reasonable without the test quality being adversely affected.

Improving Testability and Reliability of Advanced SRAM Architectures

As process technology continues to scale, the test quality, yield and reliability of modern System-on-Chips increasingly depend on their embedded SRAM blocks. Their extreme integration density in conjunction with complex manufacturing process result in subtle lithographic imperfections which demand increasingly effective test solutions to guarantee low DPPM (defective parts per million) rates while keeping test costs low. At the same time, SRAMs are particularly affected by scaling-driven reliability challenges, and addressing them by large aging guard-bands further deteriorates SRAM yield. In this work, we show that built-in circuitry integrated into modern memory architectures can resolve these challenges and eliminate or greatly reduce the need for additional design for testability logic. In particular, we propose to use assist circuits and the inherent memory self-timing mechanism to increase the coverage of small resistive-open defects as well as to specifically screen out those core-cells which are most susceptible to long-term BTI (Bias Temperature Instability) aging. A detailed fault-injection study on an industrial 28nm technology demonstrates that the range of detectable resistances for cell-internal open defects increases by up to 30 percent and potentially unreliable cells prone to BTI aging are screened out. We also suggest a test flow which applies the introduced techniques in an industrial MBIST (memory built-in self-test) environment.

Resistive Open Fault and Detection Methods for Low Power Nanometric Integrated Circuits

Resistive open fault represents degradation in conductivity within a circuit interconnection. Due to this manufacturing failure occurs in IC interconnection. Such fault causes performance failures and reliability risk. This paper presents the analysis various detection methods for resistive open faults. And detectable resistance range versus VDD varies with the test speed also observes. Depending on test speed and small delay faults Multi-VDD is required for detection of ROFs.

Circuit and Methodology for Testing Small Delay Faults in the Clock Network

A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel flush test procedure to determine if a clock network has any small delay faults. This method does not require any change of the clock network, but it does require a “special test clock signal,” which can be generated on the chip by using only standard cells. Experimental results of transistor-level simulation on benchmark circuits injected with resistive open defects in the layout show that the proposed method is capable of detecting a delay fault as small as 52.8 ps.

Low power test architecture for dynamic read destructive fault detection in SRAM

ABSTRACTDynamic Read Destructive Fault (dRDF) is the outcome of resistive open defects in the core cells of static random-access memories (SRAMs). The sensitisation of dRDF involves either performing multiple read operations or creation of number of read equivalent stress (RES), on the core cell under test. Though the creation of RES is preferred over the performing multiple read operation on the core cell, cell dissipates more power during RES than during the read or write operation. This paper focuses on the reduction in power dissipation by optimisation of number of RESs, which are required to sensitise the dRDF during test mode of operation of SRAM. The novel pre-charge architecture has been proposed in order to reduce the power dissipation by limiting the number of RESs to an optimised number of two. The proposed low power architecture is simulated and analysed which shows reduction in power dissipation by reducing the number of RESs up to 18.18%.

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs

After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware overhead and test time are proportional to the number of TSVs. In this paper, we propose a new unified test architecture for screening of TSV defects in 3-D-ICs. Depending on the number of assembled TSVs, the proposed grouping-based test architecture can effectively reduce the cumulative test time and hardware overhead without compromising the test quality.

Prebond through silicon vias test based on time-to-digital conversion}{Prebond through silicon vias test based on time-to-digital conversion

Defects in through silicon vias (TSV) not only lead to the variation of the propagation delay but also to that of the transition delay, which is more sensitive to TSV faults. A non-invasive approach for pre-bond TSV tests based on time-to-digital conversion is proposed to detect resistive open and leakage faults with picosecond accuracy. The TSVs are used as capacitive loads of their driving gates. The pulse visiting the cyclic shrinkage cells will then shrink until it vanishes completely. The shrinkage amount is digitized and compared with the expected fault-free value. The fault detection experiments are carried out with HSPICE simulations using realistic 45-nm CMOS technology models. The results show the effectiveness in the detection of resistive open defects 0.2 K$\Omega$ above and equivalent leakage resistance less than 40 M$\Omega$. . This scheme is capable of TSV quality binning; the frequencies of the input pulse or test clock have no strict limit. The estimated area overhead of the design for testability is negligible for realistic dies.

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations

Resistive-open defects in Static Random Access Memories (SRAMs) represent an important challenge for manufacturing test in submicron technologies as they may be masked by process variations, which in turn increases the number of test escapes. This paper evaluates the effectiveness of a hardware-based test approach that compares the current consumption of neighboring SRAM cells to detect resistive-open defects. The proposed approach is validated and its fault detection capabilities are analyzed for different defect sizes and taking into account process variations effects. Finally, the paper provides an evaluation of the minimum detectable resistive-open defect size for the proposed hardware-based approach under process variations effects.

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.