Abstract
As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which are caused by the thermal stress during the fabrication process. These latent defects lead to the deterioration of the electrical performance of TSVs caused by an undesired increase in the resistance-capacitance (RC) delay. For this reason, various post-bond test methodologies have been studied to improve the reliability of 3D-ICs. Cost reduction in these TSV test architectures is also currently being studied by decreasing various factors such as hardware overhead, test time, and the peak current consumption. Usually, a single test-clock-period is required to determine whether the test result contains the defective TSV. When the test result of any TSVs fails, we use another single test-clock-period to classify its defect type. In this paper, we propose a new TSV test architecture to transfer the combined test output of the test result and the specific defect type to the pad during the single test-clock-period. Our proposed test architecture also provides a reliable block-based concurrent testing to optimize the test time by dividing the die into concurrent blocks. The experimental results showed that our proposed test architecture could reduce the test time and the hardware overhead substantially by ensuring that the reasonable peak power consumption for mass production was reasonable without the test quality being adversely affected.
Highlights
Three-dimensional (3D) integration technology is an emerging fabrication technique that vertically stacks multiple device layers by using through-silicon-vias (TSVs) [1, 2]
Power consumption may reach a peak during TSV testing, and there is a perceived trade-off between the peak power consumption and the cost of automatic test equipment (ATE)
The voltages across each TSV and the peak current consumptions when the number of TSVs increased were simulated by HSPICE
Summary
Three-dimensional (3D) integration technology is an emerging fabrication technique that vertically stacks multiple device layers by using through-silicon-vias (TSVs) [1, 2]. Theses multiple device layers are vertically bonded by wafer stacking or die stacking, and each layer in the three-dimensional integrated circuit (3D-IC) is connected using TSVs and microbumps. These layers serve as interconnections and provide power improvement, high performance, and high throughput bandwidth by reducing. The post-bond test allows us to detect the device’s functional defects for 3D-ICs caused by the misalignment of TSVs, or by the high temperatures and pressures after the stacking process [19,20,21]. It is possible to provide the optimized wire overhead by using the TSV block partition method
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