Improving Testability and Reliability of Advanced SRAM Architectures

Abstract

As process technology continues to scale, the test quality, yield and reliability of modern System-on-Chips increasingly depend on their embedded SRAM blocks. Their extreme integration density in conjunction with complex manufacturing process result in subtle lithographic imperfections which demand increasingly effective test solutions to guarantee low DPPM (defective parts per million) rates while keeping test costs low. At the same time, SRAMs are particularly affected by scaling-driven reliability challenges, and addressing them by large aging guard-bands further deteriorates SRAM yield. In this work, we show that built-in circuitry integrated into modern memory architectures can resolve these challenges and eliminate or greatly reduce the need for additional design for testability logic. In particular, we propose to use assist circuits and the inherent memory self-timing mechanism to increase the coverage of small resistive-open defects as well as to specifically screen out those core-cells which are most susceptible to long-term BTI (Bias Temperature Instability) aging. A detailed fault-injection study on an industrial 28nm technology demonstrates that the range of detectable resistances for cell-internal open defects increases by up to 30 percent and potentially unreliable cells prone to BTI aging are screened out. We also suggest a test flow which applies the introduced techniques in an industrial MBIST (memory built-in self-test) environment.