Resistor-loaded Inverter Research Articles

High-Performance Tin Oxide Thin-Film Transistors Realized by Codoping and Their Application in Logic Circuits.

Tin oxide is a promising channel material, offering the advantages of being low-cost and environmentally friendly and having a wide band gap. However, despite the high electron mobility of SnO2 in bulk, the corresponding thin-film transistors (TFTs) generally exhibit moderate performance, hindering their widespread application. Herein, we proposed a codoping strategy to improve both the electrical property and the stability of SnO2 TFTs. A comparative analysis between doped and undoped SnO2 was conducted. It is observed that taking advantage of the difference in ionic radii between two dopants (indium and gallium) and the tin ions in the host lattice can effectively reduce impurity-induced strain. Additionally, we investigated the effect of codoping content on SnO2 TFTs. The optimal codoped SnO2 (TIGO) TFTs demonstrate high performance, featuring a field-effect mobility of 15.9 cm2/V·s, a threshold voltage of 0.2 V, a subthreshold swing of 0.5 V/decade, and an on-to-off current ratio of 2.2 × 107. Furthermore, the devices show high stability under both positive and negative bias stress conditions with a small threshold voltage shift of 1.8 and -1.2 V, respectively. Utilizing the TIGO TFTs, we successfully constructed a resistor-loaded unipolar inverter with a high gain of 10.76. This study highlights the potential of codoped SnO2 TFTs for advanced applications in electronic devices.

Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability

In this article, the impact of interface-trap charges (ITCs) on the DC and analog/RF parameters of gate-all-around vertical TFET (GAA-VTFET) are considered to evaluate the reliability of the device. ITCs are included at oxide/semiconductor interface of GAA-VTFET where the probability of occurrence of traps are high owing to faults in the manufacturing process. A detailed investigation is carried out by tuning the temperature, polarities and density of ITCs. It is clearly observed from TCAD based simulation results that the presence of traps alters the flat-band voltage, thereby affecting the overall performance of the device. Transfer characteristics of the device depicts that impact of traps shows more variation in the OFF-state current than the ON-current. However, presence of donor traps improves the analog/RF parameter, such as parasitic capacitances (Cgg), Transconductance (gm), cut-off frequency (fT), output resistance (Rout) etc. Furthermore, the simulation results proclaim that GAA-VTFET shows more resilient to acceptor traps than the positive traps. Moreover, by examining the influence of ambient temperature on device performance, it is revealed that the drain current in the subthreshold region (at low gate bias) is more susceptible to the degradation than the super-threshold region at elevated temperature. This is mainly due to the superiority of the trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) recombination mechanisms over the band-to-band tunneling (BTBT). When the raise in ambient temperature is tuned between minimum of 200 K to maximum of 400 K, it is observed that OFF-current increases by ∼7 times. Lastly, voltage-transfer characteristics (VTC) analysis of the resistive-load inverter clearly demonstrates that the influence of traps on the noise margin is within acceptable limits.

Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects

To improve the DC and analog/HF performance, a novel dual line tunneling based TFET (DLT-ES-TFET) with elevated source and L-shaped pocket is proposed in this manuscript. In DLT-ES-TFET, the elevated top (G1) and extended back (G2) gates overlapping the source region enhance the line tunneling of charge carriers in both vertical and horizontal directions across the source-pocket interface. TCAD-based simulation results reveal that DLT-ES-TFET offers an improvement of ∼47% and ∼54% in average subthreshold swing when it is compared with E-VTSFET and L-TFET, respectively. Furthermore, ON-current in DLT-ES-TFET is also found to be improved by an order of ∼1 as compared to other two devices. In fact, the L-shaped pocket reduces the corner effects caused by the electric filed crowding across source-channel (S-C) interface, which eventually suppresses the OFF-state leakage in the proposed DLT-ES-TFET. Moreover, enhancement in the charge carriers tunneling across S-C interface leads to a huge increment in the transconductance (∼157μs/μm) of DLT-ES-TFET, which further helps in achieving a high cut-off frequency of 12.3 GHz. Next, transient response of DLT-ES-TFET-based resistive load inverter suggests a notable improvement in peak over- and under-shoots along with propagation delay as compared to E-VTSFET and L-TFET. Lastly, interface traps and temperature analysis is also found to be in favor of the proposed DLT-ES-TFET.

Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

In this manuscript, we present a negative capacitance TFET with extended back gate-drain overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance. TCAD-based simulations reveal that DEBG-NC-TFET offers a significant enhancement in ION and SS because of a Ferroelectric (FE) layer introduced into the gate-oxide layer of the device, without deteriorating its other parameters. This work examines the effects of various factors of NC including coercive electric field (Ec) and remnant polarization (Pr) on memory window (MW) to improve the read margin of the device. With an optimum thickness of FE layer, DEBG-NC-TFET is found to offer a huge reduction in the ambipolar current (Iamb) with unchanged IOFF and ION as compared with those of symmetric gate-drain overlap (DSYG) and conventional DG-NC-TFET. The vertical component of the field induced inside the drain region increases the layer of depleted charge at the channel-drain interface, which enhances the barrier width and restricts the charge carriers from tunneling at the ambipolar state. Furthermore, incorporating back gate-drain overlap into DG-NC-TFET resolves the trade-off between parasitic capacitances and ambipolarity as overall gate capacitance is found to be reduced for DEBG-NC-TFET. Apart from reduction in gate parasitic capacitance, various HF parameters like gain–bandwidth product (GBWP) and cutoff-frequency (fT) are also found to be improved for DEBG-NC-TFET as compared to DSYG-NC-TFET. Finally, a resistive load inverter analysis shows that various parameters like propagation delay, full swing, and peak over- and undershoots are significantly improved when only the back gate overlaps the drain region of DG-NC-TFET.

GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability

AbstractFor the first time, a novel source extension heterojunction gate‐all‐around tunnel FET (SE‐GAA‐TFET) is proposed and examined using Synopsys TCAD simulator in this manuscript. SE‐GAA‐TFET is found to exhibit improved performance in terms of various analog/RF and DC parameters. As channel/source (C/S) interface and electric field exerted by gate are perpendicular to each other, radius of channel is downscaled to enhance electric filed, without reducing area of the tunneling. Furthermore, the presence of GaSb/GaAs heterojunction at C/S interface leads to reduction in the effective band overlap, which helps a great number of mobile charges to tunnel through C/S boundary at ON‐state. The consequences of variation in different geometrical metrics are evaluated to optimize the device performance. SE‐GAA‐TFET is found to offer a current switching ratio (CSR) of ~1013 along with 32.2 mV dec−1 of average sub‐threshold swing (SSAVG). Furthermore, improvement in transconductance and parasitic capacitance boost the cut‐off frequency of SE‐GAA‐TFET up to 37 GHz. Next, both positive and negative traps are introduced at S/C interface and the study reveals that there is no much deviation in parameters of the transfer characteristics like ION, SSAVG, and IOFF of SE‐GAA‐TFET. Next, proper benchmarking is done to compare the performance of the SE‐GAA‐TFET with similar devices available in literature and it is found that proposed SE‐GAA‐TFET exhibits better DC performance due to improved electrostatic behavior. Finally, SE‐GAA‐TFET is found to offer better fall time along with full‐voltage swing when deployed in a resistive load inverter.

Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs

Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs

Comparative study of Negative Capacitance Field Effect Transistors with different doped hafnium oxides

Negative Capacitance Field Effect Transistors are well known for their superior performance over MOSFET and are a viable candidate to succeed the baseline FET in time ahead. We have studied the performance of 32 nm planar MOSFET with doped hafnium dioxide as a ferroelectric material. The functioning of the NCFET is entirely dependent on the equivalence between the ferroelectric and MOS capacitance. Our simulation results clearly indicated that the Sr doped HfO2 has close capacitance matching with MOS capacitance, when compared with other dopant material (Si, Al and Zr). This also reflects in the performance parameters (drain current and transconductance characteristics) of the device designed. Also, we have designed a resistive load inverter with doped hafnium dioxide, Sr doped among them has an edge over the other ferroelectric material in terms of noise margin and static power dissipation.

Parameter Extraction from a Resistive Load Inverter Circuit Using Supervised Learning Methods

This paper presents a proposal for parameter extraction of a resistive load inverter circuit, with a Thin Film Transistor (TFT), using Artificial Neural Networks, Random Forest, Decision Trees and Support Vector Regression. Although analytical and optimization methods are usually used for this purpose, they have disadvantages such as the need for expertise or complex implementation. This work shows that these supervised learning methods are useful for this task because they can learn the parameters of the device transfer curves, obtaining a good fit between the measurements and the extracted parameters. The different methods were trained using a data set constructed from simulations performed with AIM-Spice software, where the parameters affecting different regions of the inverter characteristic curve were extracted. In the experimental stage, the Neural Networks obtained better results, with an average error rate of 6.04%. The method was also applied to real NMOS measurements and yielded minimum errors of up to 0.43%.

Energy-band engineering by 2D MXene doping for high-performance homojunction transistors and logic circuits

The homojunction based on Ti3C2Tx MXene-doped In2O3 and indium oxide as the channel layer is realized in high-performance metal oxide thin film transistors (TFTs). Doping of MXene into In2O3 results in n-type semiconductor behavior, realizing tunable work function of In2O3 from 5.11 to 4.79 eV as MXene content increases from 0 to 2 wt.%. MXene-doped In2O3-based homojunction TFT presents optimal performance with electron mobilities of greater than 27.10 cm2/(V s) at 240 °C, far exceeding the maximum mobility of 3.91 cm2/(V s) for single-layer In2O3 TFTs. The improved performance originates from boosting of a two-dimensional electron gas (2DEG) formed at carefully engineered In2O3/MXene-doped In2O3 oxide homojunction interface. Besides, the transformation in conduction mechanism leads to better stability of MXene-doped In2O3 homojunction devices compared to undoped bilayer In2O3. Low-frequency noise further illustrates that doping MXene into In2O3 helps to reduce the device trap density, demonstrating excellent electrical performance. A resistor-loaded unipolar inverter based on In2O3/0.5% MXene-In2O3 TFT has demonstrated full swing characteristics and a high gain of 13. The effective doping of MXene into constructed homojunction TFTs not only contributes to improved stability, but also provides an effective strategy for designing novel homojunction TFTs for low-cost oxide-based electronics.

Optimization of electrical performance and stability of fully solution-driven α-InGaZnO thin-film transistors by graphene quantum dots

• Fully solution-derived GQDs-IGZO TFTs based on ZrO 2 as gate dielectrics have been achieved. • GQDs-IGZO TFTs devices with optimized doping content have demonstrated improved performances, including a μ FE of 35.91 cm 2 V –1 s –1 , a higher I ON / I OFF of 5.04 × 10 8 , a smaller subthreshold swing (SS) of 0.11 V dec –1 and a smaller interfacial trap states of 1.57 × 10 12 cm −2 . • Resistor-loaded unipolar inverter based on GQDs-IGZO/ZrO x has been integrated, demonstrating good dynamic behavior and a high gain of 9.3. • LFN characteristics of GQDs-IGZO/ZrO x TFTs have suggested that the fluctuations in mobility are the noise source. This work presents solution-processed high-performance graphene quantum dots (GQDs) decorated amorphous InGaZnO (α-IGZO) thin-film transistors (TFTs) based on ZrO x as gate dielectrics. Compare with pure IGZO TFTs, GQDs-modified α-IGZO TFTs devices with optimized doping content have demonstrated better performances, including a larger field-effect mobility ( μ FE ) of 35.91 cm 2 V –1 s –1 , a higher on/off current ratio ( I ON / I OFF ) of 5.04 × 10 8 , a smaller subthreshold swing (SS) of 0.11 V dec –1 and a smaller interfacial trap states ( D it , 1.57 × 10 12 cm −2 ). Moreover, the GQDs-doped IGZO TFTs with a doping concentration of 0.5 mg ml –1 have shown excellent stability under bias stress and illumination stress conditions. To demonstrate the potential applications of α-IGZO TFTs in logic circuits, a resistor-loaded unipolar inverter based on GQDs-IGZO/ZrO x has been integrated, demonstrating good dynamic behavior and a high gain of 9.3. Low-frequency noise (LFN) characteristics of GQDs-IGZO/ZrO x TFTs have suggested that the fluctuations in mobility are the noise source. Based on all the experimental findings, it can be concluded that solution-processed GQDs-IGZO/ZrO x TFT may envision promising applications in optoelectronics.

Electrical Performance Enhancement and Low-Frequency Noise Estimation of In2O3-Based Thin Film Transistor Based on Doping Engineering

In this work, solution-derived InErO thin films were deposited to act as the channel layers of thin film transistors (TFTs). The effect of Er doping content on the morphology, oxygen defects, optical properties of indium oxide (In2O3) films, and electrical performance of InErO/Al2O3 TFTs was systematically investigated. Based on experimental results, it can be inferred that InErO-TFTs with 5% Er doping content has demonstrated improved electrical performance, including field effect mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> ) of 17.55 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2}}\,\,\cdot \,\,\text{V}^{-{1}}\,\,\cdot \,\,\text{s}^{-{1}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text{ON}}/{I} _{\text{OFF}}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.70\times 10^{{7}}$ </tex-math></inline-formula> , a subthreshold swing (SS) of 0.16 V/dec and threshold voltage shift of 0.10 and 0.09 V under positive bias stress (PBS) and negative bias stress (NBS) for 1800 s, respectively. The illumination NBS (NBIS) measurements have indicated the degraded device stability by reducing the light wavelength, which can be due to the ionization of oxygen vacancies. Low-frequency noise (LFN) characterizations on devices have shown that the interfacial density of states of In2O3-based TFTs decreases after Er doping. To demonstrate the potential applications of InErO-TFTs in logic circuits, a resistor-loaded unipolar inverter based on InErO/Al2O3 has been integrated, demonstrating good dynamic response behavior and high gain of 10. These results have indicated the great potential of solution-driven InErO-based TFTs for future applications in low-cost and high-performance electronics.

Xanthan gum-gated flexible thin-film transistor for realizing inverter functions

Theoretically, degradable bio-polysaccharide materials are good proton conductors with the potential of being used as gate dielectrics for electric-double-layer (EDL) transistors due to the abundant hydrophilic functional groups contained. In this work, xanthan gum-gated flexible EDL thin-film transistors (TFTs) were fabricated with the bio-polysaccharide material xanthan gum as the gate dielectric. The xanthan gum film prepared by solution method obtains a high specific capacitance of 2 μF/cm2 at 1 Hz, based on which the low-voltage xanthan-gated EDL TFTs exhibit good electrical properties, such as an ON/OFF ratio > 105, a carrier mobility of 14 cm2V−1s−1 along with excellent mechanical flexibility and bending stability. Furthermore, a resistor-loaded inverter based on this flexible EDL TFT has not only demonstrated excellent performance required by inverters but also realized the functions of filtering, noise reduction, and amplitude discrimination. Based on the results achieved, the xanthan gum-gated flexible EDL TFTs fabricated in this work can provide an option for the preparation of implantable & wearable smart devices.

A Complementary Logic-in-Memory Inverter From Organic-Inorganic Hybrid Transistors

Logic-in-memory (LIM) technology is an important technology that overcomes the bottleneck, a limitation of the von Neumann architecture. As described in previous reports, the LIM technology was fabricated with a resistive load inverter structure. However, there are some limitations due to the high-power consumption issue and low noise margin. As a result, the need for a LIM device with a complementary structure has emerged. Here, we propose a LIM architecture-based organic-inorganic complementary inverter circuit with a stable noise margin using a p-type floating-gate transistor memory (FGTM) and an n-type zinc-tin oxide (ZTO) thin-film transistor (TFT). We demonstrate that the output of the proposed complementary inverter circuit is determined according to the state of the FGTM memory.

Design and Functional Test of Transistor Inverter Based on Polyvinyl Alcohol and Graphene Oxide Electrolyte

Eco‐friendly “green” electronics are attracting increasing interest in recent years. For example, neural prostheses, nerve implants, drug delivery devices, and diagnostic electronics, as well as some green materials (paper, silk, and polysaccharides) with bioabsorbable and biocompatible transistors, load inverters, and other devices. Here, biodegradable polyvinyl alcohol (PVA)/graphene oxide (GO) electric double‐layer (EDL) transistors are prepared on glass substrates. PVA film treated with GO solution is used as a gate dielectric. Oxide EDL transistors show good performance. A resistive load inverter is also constructed, which shows full swing characteristics and high voltage gain at low operating voltage. The waveform conversion is realized, including the conversion from sine wave to rectangular wave, and the conversion from noise signal to two‐bit output. In addition, PVA/GO transistors can be easily dissolved in water. The proposed PVA/GO oxide transistors may have potential applications in “green” portable devices.

High-Performance Indium-Gallium-Zinc-Oxide Thin-Film Transistors with Stacked Al2O3/HfO2 Dielectrics

High-performance amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) gated by Al2O3/HfO2 stacked dielectric films are investigated. The optimized TFTs with Al2O3 (2.0 nm)/HfO2 (13 nm) stacked gate dielectrics demonstrate the best performance, including low total trap density N t, low subthreshold swing voltage, large switching ratio I ON/OFF, high mobility μ FE, and low operating voltage, equal to 1.35 × 1012 cm−2, 88 mV/dec, 5.24 × 108, 14.2 cm2/V⋅s, and 2.0 V, respectively. Furthermore, a low-voltage-operated resistor-loaded inverter has been fabricated based on such an a-IGZO TFT, showing ideal full swing characteristics and high gain of ∼27 at 3.0 V. These results indicate a-IGZO TFTs gated by optimized Al2O3/HfO2 stacked dielectrics are of great interests for low-power, high performance, and large-area display and emerging electronics.

A mechanically tunable electromagnetic wave harvester and dual-modal detector based on quasi-static van der Waals heterojunction

Electromagnetic (EM) wave harvesting and detection have many implications for self-powered human health monitoring and robot intelligence. Heterojunction-based energy harvesters and detectors can convert various forms of energy into electricity. Here, we report a mechanically tunable electromagnetic wave harvester (EMH), operated by quasi-static contact of a metal/indium gallium zinc oxide/metal van der Waals heterojunction. The proposed EMH behaves as a rectenna responding to low-frequency signals (80–400 MHz), where the electrode works as an antenna, the heterojunction between two separated layers works as a rectifying diode, and the parallel structure works as a capacitor. It is found that the pressure on the EMH plays an important role on regulating electronic interfaces and thus the output characteristics. The two output states (on/off states) of the EMH can be reversibly controlled by mechanical pressure. The proposed design and mechanism have been verified by various materials pairings and structures, which proves their great universality. The simple-structure EMH can continuously generate DC power for 10 hours without signal attenuation. It can supply power to a capacitor, a LED and a resistive load inverter, which demonstrates its application potential as an energy source. Moreover, the EMH can work as a sensor to qualitatively detect electromagnetic waves in the ambient environment and pressure. This work has proposed a novel solution to harvest and detect electromagnetic energy by van der Waals heterojunction in a mechanically controllable way, providing new possibilities for wearable electronics, intelligent robots, and Internet of Things.

Ultraviolet-Assisted Low-Thermal-Budget-Driven α-InGaZnO Thin Films for High-Performance Transistors and Logic Circuits.

Developing a low-temperature fabrication strategy of an amorphous InGaZnO (α-IGZO) channel layer is a prerequisite for high-performance oxide-based thin film transistor (TFT) flexible device applications. Herein, an ultraviolet-assisted oxygen ambient rapid thermal annealing method (UV-ORTA), which combines ultraviolet irradiation with rapid annealing treatment in an oxygen atmosphere, was proposed to realize the achievement of high-performance α-IGZO TFTs at low temperature. Experimental results have confirmed that UV-ORTA treatment has the ability to suppress defects and obtain high-quality films similar to high-temperature-annealing-treated samples. α-IGZO/HfAlO TFTs with high-performance and low-voltage operating have been achieved at a low temperature of 180 °C for 200 s, including a high μsat of 23.12 cm2 V-1 S-1, large Ion/off of 1.1 × 108, small subthreshold swing of 0.08 V/decade, and reliable stability under bias stress, respectively. As a demonstration of complex logic applications, a low-voltage resistor-loaded unipolar inverter based on an α-IGZO/HfAlO TFT has been built, demonstrating full swing characteristics and a high gain of 13.8. Low-frequency noise (LFN) characteristics of α-IGZO/HfAlO TFTs have been presented and concluded that the noise source tended to a carrier number fluctuation (ΔN) model from a carrier number and correlated mobility fluctuation (ΔN-Δμ) model. As a result, it can be inferred that the low-temperature UV-ORTA technique to improve α-IGZO thin film quality provides a facile and designable process for the integration of α-IGZO TFTs into a flexible electronic system.

Analog/RF Performance Analysis of a-ITZO Thin Film Transistor

This work reports RF and analog performance analysis of an amorphous Indium Tin Zinc Oxide thin film transistor. The various parameters affecting the performance of a-ITZO TFT like drain current, drain conductance, output resistance, transconductance, transconductance generation factor, early voltage, intrinsic gain, capacitances, cut off frequency, maximum frequency of oscillation, transconductance frequency product, gain frequency product, gain bandwidth product and gain transconductance frequency product have been closely examined. The device is further analyzed to investigate the impact of variation in physical parameters viz. dielectric material, dielectric thickness (𝐷𝑡) and temperature (T) on the RF/Analog performance. Use of high-k dielectric material in the simulated structure has resulted in low subthreshold slope (SS) of 0.62 V/decade, On voltage (𝑉𝑜𝑛) of - 0.29 V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 ratio of ~ 109, intrinsic gain (Av) of 104.5 dB and gain frequency product (GFP) of 1.86 GHz. The best results for dielectric thickness variation are obtained for Dt of 150 nm with SS of 0.22 V/decade, 𝑉𝑜𝑛 of -0.26 V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 of ~ 1010, Av of 175.69 dB and GFP of 2.39 GHz. In order to investigate device thermal reliability and stability, temperature analysis has also been done. To demonstrate the circuit level implementation of the simulated structure, a resistive load inverter circuit is simulated and analyzed for different variations (high-k, 𝐷𝑡 and T). It has also been concluded that TFT with high-k material or thinner dielectric at T=300 K provides best performance. This analysis confirms the potential of a-ITZO TFTs to realize high performance analog/RF circuits.

A no-hysteresis TIPS–pentacene:polystyrene blend-based organic field effect transistor by extruded direct ink writing and the application in a resistive load inverter circuit

Organic field effect transistors (OFETs), with the active layer made from 6,13-bis(triisopropylsilylethinyl) pentacene:polystyrene blend films, were fabricated on rigid (glass) and flexible (polyethylene terephthalate) substrates using a motor-controlled extrusion-based Direct Ink Writing printing method.

Effect of Femtosecond Laser Postannealing on a-IGZO Thin-Film Transistors

In this study, the effects of femtosecond laser postannealingwere experimentally confirmed by applying it to amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with enhanced electrical characteristics. We confirmed that a-IGZO TFTs fabricated by applying femtosecond laser annealing for 50 and 100 s improved more than as-deposited a-IGZO TFTs before annealing. However, a-IGZOTFTs irradiated formore than 150 s degraded in overall performance compared with the as-deposited a-IGZO TFTs. The result of the X-ray photoelectron spectroscopy measurement of the O1s peak on the a-IGZO thin-film indicated that the O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">total</sub> value dropped to approximately 44.3%, and the O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">total</sub> value increased to approximately 17.6% when the a-IGZO thin film was irradiated for 150 s. As a result, oxygen vacancies remained without sufficient recovery of the metal-oxygen bond, and as the electron concentration increased, the conductivity increased, and the performance of the TFT decreased due to an increase in leakage current. A resistive load inverter was fabricated by connectinga TFT irradiatedwith the femtosecond laser at the best-performing time of approximately 100 s. The result of measuring the reversal characteristics confirmed a large inversion at the rising and falling edges.