Residue Number System Research Articles

Residue Number System-Based Approach to Minimise Energy Consumption in Wireless Sensor Networks

This study harnesses the useful number properties of the residue number system (RNS) to minimise energy consumption in a wireless sensor network. In a traditional cluster-based wireless sensor network, large bit representations of aggregated packets are transmitted to the base station. However, large bit patterns of packets are slower compared to smaller bits. The proposed approach splits aggregated data into a pre-specified number of transmission channels using a moduli set. Cheap energy cost routes from the cluster heads are computed to deliver the chunked aggregated data to the base station. Forward and reverse converters are proposed to encode data into RNS and decode the RNS data that reaches the base station. MATLAB simulation is used to implement the proposed data splitting method and to evaluate network performance. The experimental results suggest that the proposed method is more effective at minimising transmission energy when compared with traditional approaches in which complete packets are transmitted.

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

The primary motive of this paper is to give the design and implementation of RNS (Residue Number System) based Area efficient and excessive-overall performance FIR filter of 4-tap, eight-tap, 16-tap of input eight bit. Additionally, RNS mathematics is a treasured device for theoretical research of the limits of fast mathematics. These proposed strategies additionally have a few additions operation, through the use of convention adder will decrease the speed of operation and additionally increase the number of logic gates. So, to conquer the one's issues we are using Ladner Fischer parallel prefix adder to lower the delay and area. First, the multiplier is designed through the use of RNS approach. In which the delay is decreased through 78.57% and power dissipation is likewise reduced to 64.65% for the RNS_PPA multiplier. A combination of those algorithms generates a brand-new structure of excessive speed and low implementation area in a single multiplier for FIR filter using Xilinx 14.7.

Enhanced cipher text-policy attribute-based encryption and serialization on media cloud data

Purpose There are various system techniques or models which are used for access control by performing cryptographic operations and characterizing to provide an efficient cloud and in Internet of Things (IoT) access control. Particularly in cloud computing environment, there is a large-scale distribution of these traditional symmetric cryptographic techniques. These symmetric cryptographic techniques use the same key for encryption and decryption processes. However, during the execution of these phases, they are under the problems of key distribution and management. The purpose of this study is to provide efficient key management and key distribution in cloud computing environment. Design/methodology/approach This paper uses the Cipher text-Policy Attribute-Based Encryption (CP-ABE) technique with proper access control policy which is used to provide the data owner’s control and share the data through encryption process in Cloud and IoT environment. The data are shared with the the help of cloud storage, even in presence of authorized users. The main method used in this research is Enhanced CP-ABE Serialization (E-CP-ABES) approach. Findings The results are measured by means of encryption, completion and decryption time that showed better results when compared with the existing CP-ABE technique. The comparative analysis has showed that the proposed E-CP-ABES has obtained better results of 2373 ms for completion time for 256 key lengths, whereas the existing CP-ABE has obtained 3129 ms of completion time. In addition to this, the existing Advanced Encryption Standard (AES) scheme showed 3449 ms of completion time. Originality/value The proposed research work uses an E-CP-ABES access control technique that verifies the hidden attributes having a very sensitive dataset constraint and provides solution to the key management problem and access control mechanism existing in IOT and cloud computing environment. The novelty of the research is that the proposed E-CP-ABES incorporates extensible, partially hidden constraint policy by using a process known as serialization procedure and it serializes to a byte stream. Redundant residue number system is considered to remove errors that occur during the processing of bits or data obtained from the serialization. The data stream is recovered using the Deserialization process.

High-performance digital image filtering architectures in the residue number system based on the Winograd method

Continuous improvement of methods for visual information registration, processing and storage leads to the need of improving technical characteristics of digital image processing systems. The paper proposes new high-performance digital filter architectures for image processing by the Winograd method with calculations performed in a residue number system with special-type moduli. To assess the performance and hardware costs of the proposed architectures, hardware simulation is carried out using a field-programmable gate array in a computer-aided design envi-ronment Xilinx Vivado 2018.3 for the target device Artix-7 xc7a200tffg1156-3. The results of hardware simulation show that the proposed filter architectures have 1.13 – 5.42 times higher performance, but require more hardware costs compared to the known methods. The results of this study can be used in the design of complex systems for image processing and analysis for their performance to be increased.

M-PolKA: Multipath Polynomial Key-Based Source Routing for Reliable Communications

Innovative traffic engineering functions and services require disrupting routing and forwarding mechanisms to be performed with low overhead over complex network topologies. Source routing (SR) is a prominent alternative to table-based routing for providing the needed expressiveness and agility by reducing the number of network states. This work proposes the M-PolKA, a topology-agnostic multipath source routing scheme and orchestration architecture for reliable communications, which explores special properties from the Residue Number System (RNS) polynomial arithmetic. A P4-based proof-of-concept is experimentally demonstrated using emulated and hardware prototypes. Also, use cases for revealing M-PolKA’s functionalities are tested in different scenarios in order to address problems, such as communication reliability improvement, agile path migration and fast failure reaction. Finally, low overhead for extra functionalities is observed when RNS-based SR is compared to traditional routing approaches.

Ultra-Low-Power Modulo Adder with Thermometer Coding for Uncertain RNS Applications

The residue numeral system (RNS) is a numerical representation of integers based on modulo values. The RNS makes computing systems more efficient in terms of speed, power, energy, area, and other considerations. In recent years, the RNS has focused on a variety of topics, including digital signal and image processing, cryptography, embedded systems (ESs), communications, and the Internet of Things (IoT), among others. Forward and reverse converters, as well as arithmetic units in the channels, all use modular addition. In low-power ESs, thermometer coding (TC) has lately been utilized to reduce uncertainty. The thermometer code (TC) is more energy-efficient and consumes less power for modulo addition as compared to binary adders. Based on TC, the proposed research develops a power-efficient modular adder. The proposed design is simulated using Cadence’s NC launch encounter tool. In comparison with conventional modular adders, the proposed modular adder consumes 40% and 35% less power for one-hot coding modulo adder and thermometer code residue (TCR) modulo adder, respectively.

A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers

PurposeFilter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.Design/methodology/approachRNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.FindingsIn this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.Originality/valueThe proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

Teaching redundant residue number system for electronics and computer students

This paper describes a study for teaching number system in a computer arithmetic course and addresses the existing gap in the current course by focusing on the characteristics of applications. A redundant residue number system (RRNS) is an efficient and innovative number system that inherits the interesting properties of both residue number system (RNS) and redundant number systems. It breaks the operands into residues by considering a moduli-set and then signifies the residues by a redundant representation. So, by limiting the carry propagation chain inside and outside the moduli, RRNS proposes more efficient arithmetic units which could be employed in digital signal processing (DSP) applications. Despite the applicability of RRNS, there is not well-organized teaching on RRNS covering the recent achievements. Besides, there is an important question for students and researchers what is the most appropriate number representation for each application category? In this paper, we present a step-by-step education process for RRNS that includes basic concepts of RNS and the redundant number system. Then we address characteristics of different applications that RRNS is suitable to be employed for them. So, the method gives a well-organized proceeding to computer arithmetic designers and students.

Generating Very Large RNS Bases

Residue Number Systems (RNS) are proven to be effective in speeding up computations involving additions and products. For these representations, there exists efficient modular reduction algorithms that can be used in the context of arithmetic over finite fields or modulo large numbers, especially when used in the context of cryptographic engineering. Their independence allows random draws of bases, which also makes it possible to protect against side-channel attacks, or even to detect them using redundancy. These systems are easily scalable, however the existence of large bases for some specific uses remains a difficult question. In this article, we present four techniques to extract RNS bases from specific sets of integers, giving better performance and flexibility to previous works in the litterature. While our techniques do not allow to solve efficiently every possible case, we provide techniques to provably and efficiently find the largest possible available RNS bases in several cases, improving the state-of-the-art on various works of the recent literature.

ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation

Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and thus has potential in privacy-preserving computing. However, efficiency is still the bottleneck. In this paper we present an area-efficient and highly unified reconfigurable multi-core architecture (named ReMCA) for full Residue Number System (RNS) variant of Fan-Vercauteren variant of Brakerski’s scheme (RNS-BFV), which employs a variable number of reconfigurable processing elements (PEs) and RNS channels. The PE unit can be flexibly configured as NTT, INTT or modular multiplier, thereby avoiding the need of other extra computational units. To reduce the computational complexity, ReMCA merges the pre/post-processing into NTT/INTT and unifies the read/write structure of NTT and INTT. Also, a conflict-free memory access pattern that doesn’t need separate bit-reversal operation is proposed to optimize the memory access. Furthermore, targeting different computational requirements, a unified hardware architecture mapping model and data memory organization model are introduced, and all the computing units that RNS-BFV involved are optimized and mapped on ReMCA. ReMCA is evaluated on a Xilinx Virtex-7 FPGA platform. Running at 250MHz, it can perform 2260 homomorphic multiplication per second. When normalized to the same parameter set, the throughput and Area-Time-Products (ATPs) of ReMCA achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.45\times \sim 5.51\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.58\times \sim 5.12\times $ </tex-math></inline-formula> improvements.

Design and Performance Analysis of High Throughput and Low Power RNS-Based FIR Filter Design on FPGA

A cost-effective finite impulse response (FIR) filter is introduced in this research work through Residue Number System (RNS). The moduli set selected provides the same benefit as that of the shift and add method. The implementation Residue Number System with reduced computational complexity, as well as high-performance finite impulse response filters that employ advanced Vivado Design Suite &amp; Artix-7 field-programmable logic (FPL) devices, are presented in this research work. For a specified 64-tap FIR filter, a classical modulo adder tree is substituted by a binary adder with enhanced accuracy pursued by a single modulo reduction stage and as a result reducing the area constraints by approximately 18%. When compared to the three-multiplier-per-tap two's complement filter, the index arithmetic complex FIR filter that is based on the Quadratic Residue Number System outperforms by approximately 75% and at the same time involving some LEs for filters with more than 8 taps. When compared to the traditional design, a 64-tap filter requires only 41% LEs.

Developing “friend or foe” protocol in residue number system code for satellite authentication

Low-earth orbit (LEO) satellite communication systems are successfully used in control and monitoring systems for the production and transportation of hydrocarbons from fields located beyond the Arctic Circle. As the number of countries engaged in the development of such fields expands, the number of groupings of LEO satellite communication systems grows as well. To prevent the possibility of intercepting and imposing a delayed command to control the intruder satellite, it is necessary to use the “friend or foe” identification system for the LEO satellite communication systems. At the same time, it is proposed to use authentication protocols with zero knowledge to ensure high imitation resistance in such systems. To increase their efficiency, the article proposes to use the codes of the residual number system (RNS). The novelty of this idea lies in the fact that the use of parallel RNS codes will reduce the time spent on performing arithmetic operations implemented in authentication protocols. This will reduce the likelihood of an intruder satellite picking up the correct response signal. Therefore, the development of an authentication protocol for LEO satellite communication systems based on RNS codes, the use of which will reduce the time for satellite identification, is an urgent task.

High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic

Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.

Low power residue number system using lookup table decomposition and finite state machine based post computation

In this paper, memory optimization and architectural level modifications are introduced for realizing the low power &lt;span lang="EN-US"&gt;residue number system (RNS) with improved flexibility for electroencephalograph (EEG) signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance finite impulse response (FIR) filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed lookup table (LUT) model which can produce the results without using any post accumulation process. The reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is established to develop and execute pre-calculated inverters for various module sets. Therefore, the proposed LUT-decomposition with RNS multiplication-based post-accumulation technology provides a high-performance FIR filter architecture that allows different frequency response configuration elements. Experimental results shows the superior performance of decomposing LUT-based direct reverse conversion over other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations. When compared with the conventional RNS FIR design with the proposed FSM based decomposed RNS FIR, the logic elements (LEs) were reduced by 4.57%, the frequency component is increased by 31.79%, number of LUTs is reduced by 42.85%, and the power dissipation was reduced by 13.83%.&lt;/span&gt;

Secured Paillier Homomorphic Encryption Scheme Based on the Residue Number System

In this paper, we present an improved Paillier Cryptosystem for a secured data transmission based on the Residue Number System (RNS). The current state of Paillier Cryptosystem allows the computation of the plaintext from the cipher text without solving its security assumption of Decisional Composite Residuosity or the knowledge of its private keys under mathematical attacks. The proposed RNS based cryptosystem involving two stages of encryption and two stages of decryption has never been adequately studied before. This paper attempts to solve by introducing two stages of encryption and two stages of decryption. The first stage of the encryption process maintains the traditional Paillier encryption process and the second stage process is the encryption using the recommended moduli set – by the RNS Forward converter. At the first stage of the decryption process, our proposed RNS based reverse converter is adopted and finally, the traditional Paillier decryption process will be used at the second stage of the decryption process. Because the entire encryption technique is randomized, it can withstand chosen bruteforce attacks. The suggested algorithm's security study reveals that it has a wide key space ( , a high level resistance to key sensitivity attacks, and an acceptable level of resilience. In terms of security, it has been discovered that the proposed system outperforms the present algorithm.

Error-Correction Coding Using Polynomial Residue Number System

There has been a tendency to use the theory of finite Galois fields, or GF(2n), in cryptographic ciphers (AES, Kuznyechik) and digital signal processing (DSP) systems. It is advisable to use modular codes of the polynomial residue number system (PRNS). Modular codes of PRNS are arithmetic codes in which addition, subtraction and multiplication operations are performed in parallel on the bases of the code, which are irreducible polynomials. In this case, the operands are small-bit residues. However, the independence of calculations on the bases of the code and the lack of data exchange between the residues can serve as the basis for constructing codes of PRNS capable of detecting and correcting errors that occur during calculations. The article will consider the principles of constructing redundant codes of the polynomial residue number system. The results of the study of codes of PRNS with minimal redundancy are presented. It is shown that these codes are only able to detect an error in the code combination of PRNS. It is proposed to use two control bases, the use of which allows us to correct an error in any residue of the code combination, in order to increase the error-correction abilities of the code of the polynomial residue number system. Therefore, the development of an algorithm for detecting and correcting errors in the code of the polynomial residue number system, which allows for performing this procedure based on modular operations that are effectively implemented in codes of PRNS, is an urgent task.

Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the preprocessing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2n +1) adder design shows a 24.5% saving in area-delay-product (ADP).

An Evaluation of Power Side-Channel Resistance for RNS Secure Logic

In this paper, residue number system (RNS) based logic is proposed as a protection against power side-channel attacks. Every input to RNS logic is encrypted as a share of the original input in the residue domain through modulus values. Most existing countermeasures enhance side-channel privacy by making the power trace statistically indistinguishable. The proposed RNS logic provides cryptographic privacy that also offers side-channel resistance. It also offers side-channel privacy by mapping different input bit values into similar bit encodings for the shares. This property is also captured as a symmetry measure in the paper. This side-channel resistance of the RNS secure logic is evaluated analytically and empirically. An analytical metric is developed to capture the conditional probability of the input bit state given the residue state visible to the adversary, but derived from hidden cryptographic secrets. The transition probability, normalized variance, and Kullback–Leibler (KL) divergence serve as side-channel metrics. The results show that our RNS secure logic provides better resistance against high-order side-channel attacks both in terms of power distribution uniformity and success rates of machine learning (ML)-based power side-channel attacks. We performed SPICE simulations on Montgomery modular multiplication and Arithmetic-style modular multiplication using the FreePDK 45 nm Technology library. The simulation results show that the side-channel security metrics using KL divergence are 0.0204 for Montgomery and 0.0020 for the Arithmetic-style implementation. This means that Arithmetic-style implementation has better side-channel resistance than the Montgomery implementation. In addition, we evaluated the security of the AES encryption with RNS secure logic on a Spartan-6 FPGA Board. Experimental results show that the protected AES circuit offers 79% higher resistance compared to the unprotected AES circuit.

Designing of fault-tolerant computer system structures using residue number systems

AbstractThis article discusses computing systems that operate in residue number systems (RNSs). The main direction of improving computer systems (CSs) is increasing the speed of implementation of arithmetic operations and the reliability of their functioning. Encoding data in RNS solves the problem of optimal redundancy, i.e., the creation of such computing systems provides maximum reliability with restrictions on weight and size characteristics. This article proposes new structures of fault-tolerant CSs operating in RNS in the case of the application with an active fault-tolerant method. The use of the active fault-tolerant method (dynamic redundancy) in the RNSs provides higher reliability. In addition, with an increase in the digits of CSs, the efficiency of using the proposed structures increases.

Secured Paillier Homomorphic Encryption Scheme Based on the Residue Number System

Secured Paillier Homomorphic Encryption Scheme Based on the Residue Number System