Design and Performance Analysis of High Throughput and Low Power RNS-Based FIR Filter Design on FPGA

Abstract

A cost-effective finite impulse response (FIR) filter is introduced in this research work through Residue Number System (RNS). The moduli set selected provides the same benefit as that of the shift and add method. The implementation Residue Number System with reduced computational complexity, as well as high-performance finite impulse response filters that employ advanced Vivado Design Suite & Artix-7 field-programmable logic (FPL) devices, are presented in this research work. For a specified 64-tap FIR filter, a classical modulo adder tree is substituted by a binary adder with enhanced accuracy pursued by a single modulo reduction stage and as a result reducing the area constraints by approximately 18%. When compared to the three-multiplier-per-tap two's complement filter, the index arithmetic complex FIR filter that is based on the Quadratic Residue Number System outperforms by approximately 75% and at the same time involving some LEs for filters with more than 8 taps. When compared to the traditional design, a 64-tap filter requires only 41% LEs.