Residue Number System Research Articles

Zero-Aware Low-Precision RNS Scaling Scheme

Scaling is one of the complex operations in the Residue Number System (RNS). This operation is necessary for RNS-based implementations of deep neural networks (DNNs) to prevent overflow. However, the state-of-the-art RNS scalers for special moduli sets consider the 2k modulo as the scaling factor, which results in a high-precision output with a high area and delay. Therefore, low-precision scaling based on multi-moduli scaling factors should be used to improve performance. However, low-precision scaling for numbers less than the scale factor results in zero output, which makes the subsequent operation result faulty. This paper first presents the formulation and hardware architecture of low-precision RNS scaling for four-moduli sets using new Chinese remainder theorem 2 (New CRT-II) based on a two-moduli scaling factor. Next, the low-precision scaler circuits are reused to achieve a high-precision scaler with the minimum overhead. Therefore, the proposed scaler can detect the zero output after low-precision scaling and then transform low-precision scaled residues to high precision to prevent zero output when the input number is not zero.

Algorithm for Constructing Modular Projections for Correcting Multiple Errors Based on a Redundant Residue Number System Using Maximum Likelihood Decoding

Algorithm for Constructing Modular Projections for Correcting Multiple Errors Based on a Redundant Residue Number System Using Maximum Likelihood Decoding

Enhanced image security using residue number system and new Arnold transform

This paper aims to improve the image scrambling and encryption effect in traditional two-dimensional discrete Arnold transform by introducing a new Residue number system (RNS) with three moduli and the New Arnold Transform. The study focuses on improving the classical discrete Arnold transform with quasi-affine properties, applying image scrambling and encryption research. The design of the method is explicit to three moduli set {2n, 2n+1+1, 2n+1-1}. These moduli set includes equalized and shapely moduli leading to the effective execution of the residue to binary converter. The study employs an arithmetic residue to the binary converter and an improved Arnold transformation algorithm. The encryption process uses MATLAB to accept a digital image input and subsequently convert the image into an RNS representation. The images are connected as a group. The resulting encrypted image uses the Arnold transformation algorithm. The encrypted image is used as input at decryption using the anti-Arnold (Reverse Arnold) transformation algorithm to convert the picture to the original RNS (original pixel value). Then the RNS was used to retransform the original RNS to its binary form. Security analysis tests, like histogram analysis, keyspace, key sensitivity, and correlation coefficient analysis, were administered on the encrypted image. Results show that the hybrid system can use the improved Arnold transform algorithm with better security and no constraint on image width and size.

METHOD FOR DIAGNOSING DATA ERRORS OF A COMPUTER SYSTEM FUNCTIONING IN THE SYSTEM OF RESIDUAL CLASSES

The subject of the article is the development of a method for diagnosing data errors of a computer system functioning in the residue number system (RNS). This method is based on the tabular principle of data diagnostics operation implementation. The purpose of the article is to reduce the time of performing the operation of diagnosing the data of a computer system that functions in the RNS in the dynamics of the computational process. Tasks: to analyze the possible application of RNS as a number system in computer data processing systems; to investigate existing methods of data diagnostics and identify possible shortcomings in data diagnostics in the dynamics of the computational process with the introduction of minimal information redundancy; to develop a method for diagnosing the data presented in the RNS, which is based on the tabular principle of the implementation of the diagnostic operation. Research methods: methods of analysis and synthesis of computer systems, number theory, coding theory in RNS. The following results were obtained. The work shows that the data diagnostics is carried out after the control operation has been performed. To carry out the operation of diagnosing data in the RNS, when one-time errors occur, methods for determining an alternative set (AS) of numbers are used. In this case, the main disadvantage of the considered methods is the considerable time required to determine the AS. To reduce the time for determining the AC numbers in the work, the method for diagnosing data in the RNS has been improved. Improvement of the method involves the compilation of a table (the first stage) of correspondence to each correct number of a possible set of incorrect numbers when one-time errors occur in the data. Based on the analysis of the contents of the table of the first stage, a table (of the second stage) is drawn up of the correspondence of each incorrect number to the possible values of the correct numbers. Conclusions. The use of the improved method increases the efficiency of diagnostics of the data presented in the RNS by reducing the time for determining the AC numbers. This is achieved by quickly fetching pre-calculated AC table values.

Quadruples for Residue Number Systems with Sum of Quotients a Power of a Prime

We investigate Residue Number Systems (RNS) of special type which were recently shown to be useful for some type of computations in embedded systems. We develop an algorithm for derivation of all quadruples for RNS under investigation subject to certain restrictions.

Sign Detection and Signed Integer Comparison for the 3-Moduli Set {2^n±1,2^(n+k)}

Comparison, division and sign detection are considered complicated operations in residue number system (RNS). A straightforward solution is to convert RNS numbers into binary formats and then perform complicated operations using conventional binary operators. If efficient circuits are provided for comparison, division and sign detection, the application of RNS can be extended to the cases including these operations.For RNS comparison in the 3-moduli set , we have only found one hardware realization. In this paper, an efficient RNS comparator is proposed for the moduli set which employs sign detection method and operates more efficient than its counterparts. The proposed sign detector and comparator utilize dynamic range partitioning (DRP), which has been recently presented for unsigned RNS comparison. Delay and cost of the proposed comparator are lower than the previous works and makes it appropriate for RNS applications with limited delay and cost.

Magnitude Comparison and Sign Detection based on the 4-Moduli Set {2n+1, 2n−1, 2n+3, 2n−3}

The 4-moduli set residue number system (RNS),{2n+1, 2n−1, 2n+3, 2n−3}, with a wide dynamic range, has recently been proposed as a balanced 4-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this 4-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite 14.7 tool and the Spartan6 family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a 46% and 28% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.

Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA

For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.

Attacks and Defenses for Single-Stage Residue Number System PRNGs

This paper explores the security of a single-stage residue number system (RNS) pseudorandom number generator (PRNG), which has previously been shown to provide extremely high-quality outputs when evaluated through available RNG statistical test suites or in using Shannon and single-stage Kolmogorov entropy metrics. In contrast, rather than blindly performing statistical analyses on the outputs of the single-stage RNS PRNG, this paper provides both white box and black box analyses that facilitate reverse engineering of the underlying RNS number generation algorithm to obtain the residues, or equivalently key, of the RNS algorithm. We develop and demonstrate a conditional entropy analysis that permits extraction of the key given a priori knowledge of state transitions as well as reverse engineering of the RNS PRNG algorithm and parameters (but not the key) in problems where the multiplicative RNS characteristic is too large to obtain a priori state transitions. We then discuss multiple defenses and perturbations for the RNS system that fool the original attack algorithm, including deliberate noise injection and code hopping. We present a modification to the algorithm that accounts for deliberate noise, but rapidly increases the search space and complexity. Lastly, we discuss memory requirements and time required for the attacker and defender to maintain these defenses.

A new sign detection design for the residue number system based on quantum-dot cellular automata

A new sign detection design for the residue number system based on quantum-dot cellular automata

Effective Error Control Scheme in Real-Time Wireless Sensor Networks

Wireless Sensor Networks (WSNs) subsist on network of huge numbers of hubs that are distributed in unfriendly environments used for habitat monitoring and to observe changes in phenomena. These hubs are susceptible to faults such as energy exhaustion, hardware glitches, communication link errors, malicious attacks, which may lead to errors in message delivery. However, these systems are typically utilized to convey vital information in remote places. Thus, efficient error identification and correction is thereby required in order to maintain the accuracy of the received message. This paper aimed at designing high speed reverse converter for effective error control codes using Redundant Residue Number System in order to enhance the accuracy of messages delivered for real-time WSNs. In order to attain a greater error correction, a reverse converter which was based on Mixed Radix Conversion was designed for the moduli set {2n+1-1, 2n, 2n-1}. In addition to this moduli, an extra redundant moduli set{2n+1+3, 22n - 3} is also designed for higher correctness. For correction and identification of corrupted values in the original data, maximum likelihood was used. The results obtained show that the suggested moduli set offers low energy utilization and consistency of the received message in real time WSNs.

FPGA Implementation of high speed-low energy RNS based Reconfigurable-FIR Filter for Cognitive Radio Applications

The Finite impulse response (FIR) filter is prominently employed in many digital signal processing (DSP) systems for various applications. In this paper, we present a high-performance RNS based FIR filter design for filtration in SDR applications. In general, the residue number system (RNS) gives significant metrics over FIR implementation with its inherent parallelism and data partitioning mechanism. But with increased bit width cause considerable performance trade-off due to both residue computation and reverse conversion. In this paper optimized Residue Number System (RNS) arithmetic is proposed which includes distributed arithmetic based residue computation during RNS multiplication followed by speculative delay optimized reverse computation to mitigate the FIR filter trade-off characteristics with filter length. The proposed RNS design utilizes built-in RAMs block present in the devices of FPGA to accomplish the process of reverse conversion and to store pre-computational values. A distinctive feature of the proposed FIR filter implementation with core optimized RNS is to minimize hardware complexity overhead with the improved operating speed. Initially, fetal audio signal detection is carried out to validate the functionality of FIR filter core and FPGA hardware synthesis is carried out for various input word size and FIR length. From the experimental, it is proved that the trade-off exists in conventional RNS FIR over filter length is narrow down along with considerable complexity reduction with our proposed optimized RNS system.

Data Hiding in Digital Image for Efficient Information Safety Based on Residue Number System

The mass dispersal of digital communication requires the special measures of safety. The need for safe communication is greater than ever before, with computer networks now managing almost all of our business and personal affairs. Information security has become a major concern in our digital lives. The creation of new transmission technologies forces a specific protection mechanisms strategy particularly in data communication state.
 We proposed a steganography method in this paper, which reads the message, converting it into its Residue Number System equivalent using the Chinese Remainder Theorem (CRT), encrypting it using the Rivest Shamir Adleman (RSA) algorithm before embedding it in a digital image using the Least Significant Bit algorithm of steganography and then transmitting it through to the appropriate destination and from which the information required to reconstruct the original message is extracted. These techniques will enhance the ability to hide data and the hiding of ciphers in steganographic image and the implementation of CRT will make the device more efficient and stronger. It reduces complexity problems and improved execution speed and reduced the time taken for processing the encryption and embedding competencies.

High Precision Multiplier for RNS {2n−1,2n,2n+1}

The Residue Number System (RNS) is a non-weighted number system. Benefiting from its inherent parallelism, RNS has been widely studied and used in Digital Signal Processing (DSP) systems and cryptography. However, since the dynamic range in RNS has been fixed by its moduli set, it is hard to solve the overflow problem, which can be easily solved in Two’s Complement System (TCS) by expanding the bit-width of it. For the multiplication in RNS, the traditional way to deal with overflow is to scale down the inputs so that the result can fall in its dynamic range. However, it leads to a loss of precision. In this paper, we propose a high-precision RNS multiplier for three-moduli set 2n−1,2n,2n+1, which is the most used moduli set. The proposed multiplier effectively improves the calculation precision by adding several compensatory items to the result. The compensatory items can be obtained directly from preceding scalers with little extra effort. To the best of our knowledge, we are the first one to propose a high-precision RNS multiplier for the moduli set 2n−1,2n,2n+1. Simulation results show that the proposed RNS multiplier can get almost the same calculation precision as the TCS multiplier with respect to Mean Square Error (MSE) and Signal-to-Noise Ratio(SNR), which outperforms the basic scaling RNS multiplier about 2.6–3 times with respect to SNR.

New Algorithm for Reverse Conversion in Residue Number System

Reverse conversion is an important exercise in achieving the properties of Residue Number System (RNS). Current algorithms available for reverse conversion exhibits greater computational overhead in terms of speed and area. In this paper, we have developed a new algorithm for reverse conversion for two-moduli set and three-moduli set that are very simple and with fewer multiplicative inverse operations than there are in the traditional algorithms like the Chinese Remainder Theorem (CRT) and Mixed Radix Conversion (MRC).

The Study of Monotonic Core Functions and Their Use to Build RNS Number Comparators

A non-positional residue number system (RNS) enjoys particularly efficient implementation of addition and multiplication, but non-modular arithmetic operations in RNS-like number comparison are known to be difficult. In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on using the core function for which it was shown that it must be monotonic to allow for RNS number comparison. The conditions of the monotonicity of the core function were formulated, which also ensured the minimal range of the core function (essential to obtain the best characteristics of the comparator). The best choice is a core function in which only one coefficient corresponding to the largest modulus is set to 1 whereas all other coefficients are set to 0. It is also shown that the already known diagonal function is nothing else but the special case of the core function with all coefficients set to 1. Performance evaluation suggests that the new comparator uses less hardware and in some cases also introduces smaller delay than its counterparts based on diagonal function. The potential applications of the new comparator include some recently developed homomorphic encryption algorithms implemented using RNS.

Computationally Efficient Approach to Implementation of the Chinese Remainder Theorem Algorithm in Minimally Redundant Residue Number System

In this paper, we deal with the critical problem of performing non-modular operations in the Residue Number System (RNS). The Chinese Remainder Theorem (CRT) is widely used in many modern computer applications. Throughout the article, an efficient approach for implementing the CRT algorithm is described. The structure of the rank of an RNS number, a principal positional characteristic of the residue code, is investigated. It is shown that the rank of a number can be represented by a sum of an inexact rank and a two-valued correction to it. We propose a new variant of minimally redundant RNS, which provides low computational complexity for the rank calculation, and its effectiveness analyzed concerning conventional non-redundant RNS. Owing to the extension of the residue code, by adding the excess residue modulo 2, the complexity of the rank calculation goes down from Oleft (k^{2}right ) to Oleft (kright ) with respect to required modular addition operations and lookup tables, where k equals the number of non-redundant RNS moduli.

High Performance Digital Filtering on Modified Multiply and Accumulate Unit in Residue Number System with Special Type of Moduli

The paper proposes the implementation of digital filtering using residue number system and the modified truncated multiply and accumulate unit. The work was carried out a theoretical analysis of digital filters using residue number system arithmetic and implemented hardware simulation on FPGA. FPGA hardware simulation results show that the use of residue number system allows to increase the frequency of digital filters up to about 4 times and hardware costs reduce up to 3 times compared to using a common positional number system. The obtained results open up the possibility for efficient hardware implementation of digital filters on modern devices (FPGA, ASIC and etc.) to solve practical problems, such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo {2<sup>n </sup>- 1, 2<sup>n</sup>, 2<sup>n</sup> + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.

A hierarchical secure data aggregation method using the dragonfly algorithm in wireless sensor networks

A wireless sensor network (WSN) consists of a set of sensor nodes that are widely scattered in inaccessible areas. When deployed in large areas, WSNs generate a large volume of the data. Therefore, efficient methods are needed to process the data. One solution to minimize traffic on large-scale wireless sensor networks is to use data aggregation schemes. In this paper, a secure data aggregation method is proposed. The proposed secure data aggregation scheme has three phases: intra-cluster data aggregation, inter-cluster data aggregation, and data transfer. In the intra-cluster data aggregation phase, a fuzzy scheduling system is designed to adjust the appropriate data transmission rates of the cluster member nodes. In the inter-cluster data aggregation phase, an aggregation tree is created between the cluster head nodes. The dragonfly algorithm (DA) is used to find the optimal aggregation tree between cluster head nodes. In the data transfer phase, the columnar transposition cipher method is used to establish a secure connection between cluster member nodes and their cluster head node. Also, a symmetric and lightweight encryption method based on the residue number system (RNS) is utilized to provide secure communications between the cluster head nodes. We modify RNS and call it RNS+. Finally, the simulation results of the proposed scheme are compared to three data aggregation methods including Sign-share, Sham-share, and RCDA. The results show that the proposed data aggregation scheme outperforms other data aggregation methods in terms of network lifetime, delay and packet delivery rate.