Required Hardware Resources Research Articles

Digital Aided Analog Data Acquisition for Telemetry

This paper tackles the limitations in the current data acquisition system through the integration of a equiripple Finite Impulse Response (FIR) filter. The inclusion of this digital filter eliminates the necessity for physical component alterations, thereby increasing the system’s adaptability and versatility in telemetry applications. The FIR filter’s ability to adjust passband, stopband, and sampling frequencies allows for seamless reconfiguration without the need for hardware modifications, representing a substantial enhancement compared to the constraints of the previous system. Additionally, the equiripple design guarantees minimal variations in passband and stopband ripples, thereby optimizing overall filter performance. An important aspect of the proposed solution is the implementation of shift-and-add multiplier architecture for the FIR filter, which contributes to a reduction in hardware complexity and resource requirements, ultimately leading to a more efficient system. The adoption of MATLAB’s robust filter design tools, coupled with subsequent verification through SIMULINK simulations, has played a pivotal role in successfully realizing the proposed design. To sum up, this project has efficiently addressed the identified issues by introducing a reconfigurable FIR filter solution that not only enhances the flexibility, performance, and user friendliness of the data acquisition system in telemetry applications but also showcases the potential for broader applications in various signal processing domain.

Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes

The inherent degeneracy of quantum low-density parity-check codes poses a challenge to their decoding, as it significantly degrades the error-correction performance of classical message-passing decoders. To improve their performance, a post-processing algorithm is usually employed. To narrow the gap between algorithmic solutions and hardware limitations, we introduce a new post-processing algorithm with a hardware-friendly orientation, providing error correction performance competitive to the state-of-the-art techniques. The proposed post-processing, referred to as check-agnosia, is inspired by stabilizer-inactivation, while considerably reducing the required hardware resources, and providing enough flexibility to allow different message-passing schedules and hardware architectures. We carry out a detailed analysis for a set of Pareto architectures with different tradeoffs between latency and power consumption, derived from the results of implemented designs on an FPGA board. We show that latency values close to one microsecond can be obtained on the FPGA board, and provide evidence that much lower latency values can be obtained for ASIC implementations. In the process, we also demonstrate the practical implications of the recently introduced t-covering layers and random-order layered scheduling.

Investigation on Vision System: Digital FPGA Implementation in Case of Retina Rod Cells.

The development of prostheses and treatments for illnesses and recovery has recently been centered on hardware modeling for various delicate biological components, including the nervous system, brain, eyes, and heart. The retina, being the thinnest and deepest layer of the eye, is of particular interest. In this study, we employ the Nyquist-Based Approximation of Retina Rod Cell (NBAoRRC) approach, which has been adapted to utilize Look-Up Tables (LUTs) rather than original functions, to implement rod cells in the retina using cost-effective hardware. In modern mathematical models, numerous nonlinear functions are used to represent the activity of these cells. However, these nonlinear functions would require a substantial amount of hardware for direct implementation and may not meet the required speed constraints. The proposed method eliminates the need for multiplication functions and utilizes a fast, cost-effective rod cell device. Simulation results demonstrate the extent to which the proposed model aligns with the behavior of the primary rod cell model, particularly in terms of dynamic behavior. Based on the results of hardware implementation using the Field-Programmable Gate Arrays (FPGA) board Virtex-5, the proposed model is shown to be reliable, consume 30 percent less power than the primary model, and have reduced hardware resource requirements. Based on the results of hardware implementation using the reconfigurable FPGA board Virtex-5, the proposed model is reliable, uses 30% less power consumption than the primary model in the worth state of the set of approximation method, and has a reduced hardware resource requirement. In fact, using the proposed model, this reduction in the power consumption can be achieved. Finally, in this article, by using the LUT which is systematically sampled (Nyquist rate), we were able to remove all costly operators in terms of hardware (digital) realization and achieve very good results in the field of digital implementation in two scales of network and single neuron.

An overview of the emotional brain-computer interface

This paper provides a comprehensive review of current research advances in emotional brain-computer interfaces. We introduce an approach to classifying emotions and highlight the two main datasets used for emotion recognition (DEAP and SEED). Subsequently, an extensive analysis of existing emotion recognition methods, both traditional and deep neural network methods, is presented. Finally, we explore the potential benefits of using transfer learning techniques to improve the performance of emotion recognition methods. Various deep neural network models exhibit redundant neural units and complexity, while facing challenges such as reduced computational power and reaction speed, increased storage requirements, and hardware dependency. The authors propose to integrate learned neural network pruning algorithms to simplify complex models, minimise hardware resource requirements without compromising accuracy, and improve operational capabilities with improved discriminants.

SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA

This paper proposes an unconventional architecture and algorithm for implementing reservoir computing on FPGA. An architecture-oriented algorithm with improved throughput and architecture designed to reduce memory and hardware resource requirements are presented. The proposed architecture exhibits good performance in terms of benchmarks for reservoir computing. A prediction accelerator for reservoir computing that operates on 55.45 mW at 450 K fps with <3000 LEs is realized by implementing the architecture on FPGA. The proposed approach presents a novel FPGA implementation of reservoir computing focussing on both algorithms and architecture that may serve as a basis for applications of AI at network edge.

Hardware Implementations of Elliptic Curve Cryptography Using Shift-Sub Based Modular Multiplication Algorithms

Elliptic curve cryptography (ECC) over prime fields relies on scalar point multiplication realized by point addition and point doubling. Point addition and point doubling operations consist of many modular multiplications of large operands (256 bits for example), especially in projective and Jacobian coordinates which eliminate the modular inversion required in affine coordinates for every point addition or point doubling operation. Accelerating modular multiplication is therefore important for high-performance ECC. This paper presents the hardware implementations of modular multiplication algorithms, including (1) interleaved modular multiplication (IMM), (2) Montgomery modular multiplication (MMM), (3) shift-sub modular multiplication (SSMM), (4) SSMM with advance preparation (SSMMPRE), and (5) SSMM with CSAs and sign detection (SSMMCSA) algorithms, and evaluates their execution time (the number of clock cycles and clock frequency) and required hardware resources (ALMs and registers). Experimental results show that SSMM is 1.80 times faster than IMM, and SSMMCSA is 3.27 times faster than IMM. We also present the ECC hardware implementations based on the Secp256k1 protocol in affine, projective, and Jacobian coordinates using the IMM, SSMM, SSMMPRE, and SSMMCSA algorithms, and investigate their cost and performance. Our ECC implementations can be applied to the design of hardware security module systems.

An Adaptive Filter Based Motion Artifact Cancellation Technique Using Multi-Wavelength PPG for Accurate HR Estimation.

This article presents a motion artifact (MA) cancellation technique for accurate photoplethysmography (PPG)-based heart rate (HR) estimation. The MA is canceled using two PPG signals, measured with closely placed red and green LEDs. The proposed technique utilizes the characteristics of the two PPG signals: the high correlation in MA and their different AC/DC ratios. These characteristics allow the MA to be canceled by an adaptive filter while preserving the AC components. In addition, the use of the sign-sign least mean square (SS-LMS) algorithm for the adaptive filter minimizes the hardware resource requirements. To validate the technique, a prototype was implemented and experiments were conducted with six subjects performing three types of movements: walking, running, and squatting. The proposed MA cancellation method significantly reduced the mean absolute error (MAE) in HR estimation, from 9.83 bpm to 1.48 bpm on average, compared to the conventional bandpass filtered green PPG.

ReplaceNet: real-time replacement of a biological neural circuit with a hardware-assisted spiking neural network.

Recent developments in artificial neural networks and their learning algorithms have enabled new research directions in computer vision, language modeling, and neuroscience. Among various neural network algorithms, spiking neural networks (SNNs) are well-suited for understanding the behavior of biological neural circuits. In this work, we propose to guide the training of a sparse SNN in order to replace a sub-region of a cultured hippocampal network with limited hardware resources. To verify our approach with a realistic experimental setup, we record spikes of cultured hippocampal neurons with a microelectrode array (in vitro). The main focus of this work is to dynamically cut unimportant synapses during SNN training on the fly so that the model can be realized on resource-constrained hardware, e.g., implantable devices. To do so, we adopt a simple STDP learning rule to easily select important synapses that impact the quality of spike timing learning. By combining the STDP rule with online supervised learning, we can precisely predict the spike pattern of the cultured network in real-time. The reduction in the model complexity, i.e., the reduced number of connections, significantly reduces the required hardware resources, which is crucial in developing an implantable chip for the treatment of neurological disorders. In addition to the new learning algorithm, we prototype a sparse SNN hardware on a small FPGA with pipelined execution and parallel computing to verify the possibility of real-time replacement. As a result, we can replace a sub-region of the biological neural circuit within 22 μs using 2.5 × fewer hardware resources, i.e., by allowing 80% sparsity in the SNN model, compared to the fully-connected SNN model. With energy-efficient algorithms and hardware, this work presents an essential step toward real-time neuroprosthetic computation.

Data-Mining-Based Hardware-Efficient Neural Network Controller for DC–DC Switching Converters

For the exiting neural network (NN)-based controllers, since the training data are not optimized using different control algorithms, their controlling performance improvements are limited. This paper proposes a data-mining-based hardware-efficient NN controller for DC&#x2013;DC switching converters. Firstly, the data mining strategy for NN controllers is proposed to optimize the training data. In data mining process, the optimal control data are selected from different control algorithms to create an optimized dataset for training NN controller. In addition, to reduce the hardware resources, the structure of a hardware-efficient NN controller is proposed, which comprises coarse-tuning NN (NN-ct) and fine-tuning NN (NN-ft) controllers, and the switching between two NN controllers is conducted based on the output voltage variation. The NN-ct and NN-ft controllers are trained using the optimized fine-tuning and coarse-tuning sub-datasets, respectively. By switching the weights and biases and disabling some hidden-layer nodes, two separate NN controllers can share some hardware resources, thus reducing the hardware cost without sacrificing the performance. The simulation and experimental results demonstrate that data-mining-based NN controller has better performance than other NN controllers. Furthermore, the hardware resource requirement of a hardware-efficient NN controller can be reduced by at least 17% when compared with an ordinary NN controller.

Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

AbstractElliptic curve point multiplication is the main primitive required in almost all security schemes using elliptic curve cryptography (ECC). It is the leading computationally intensive operation that sets the overall performance of the associated cryptosystem. This work presents a highly novel area–time efficient elliptic curve point multiplier over a general prime field . It is based on an efficient radix‐23 parallel multiplier, which performs a ‐bit multiplication in clock cycles. On the system level, the twisted Edwards curves with unified point addition using projective coordinates are adopted, where an efficient scheduling technique is presented to schedule several operations on deployed modular arithmetic units. Due to the introduced optimization at different stages of the design, latency, hardware resource requirement, and total clock cycle count are reduced significantly. Synthesis, and implementation of the proposed design over different Xilinx FPGA platforms are completed using the Xilinx ISE Design Suite tool for key sizes of 192, 224, and 256 bits. The 256‐bit Xilinx Virtex‐7 FPGA implementation reveals that it completes a single point multiplication operation in 0.8 ms and occupies 6.7K FPGA slices in a clock cycle count of 132.2K. It produces significantly better area–time product and throughput per slice than the contemporary designs. The proposed design also has the potential to counter simple power analysis and timing attacks. Thus, it is an elegant solution to develop ECC‐based cryptosystems for applications, where both speed and hardware resource consumption are important.

YOLOv5s-T: A Lightweight Small Object Detection Method for Wheat Spikelet Counting

Utilizing image data for yield estimation is a key topic in modern agriculture. This paper addresses the difficulty of counting wheat spikelets using images, to improve yield estimation in wheat fields. A wheat spikelet image dataset was constructed with images obtained by a smartphone, including wheat ears in the flowering, filling, and mature stages of reproduction. Furthermore, a modified lightweight object detection method, YOLOv5s-T, was incorporated. The experimental results show that the coefficient of determination (R2) between the predicted and true values of wheat spikelets was 0.97 for the flowering stage, 0.85 for the grain filling stage, and 0.78 for the mature stage. The R2 in all three fertility stages was 0.87, and the root mean square error (RMSE) was 0.70. Compared with the original YOLOv5s algorithm, the spikelet detection counting effect of YOLOv5s-T was not reduced. Meanwhile, the model size was reduced by 36.8% (only 9.1 M), the GPU memory usage during the training process was reduced by 0.82 GB, the inference time was reduced by 2.3 ms, the processing time was reduced by 10 ms, and the calculation amount was also reduced. The proposed YOLOv5s-T algorithm significantly reduces the model size and hardware resource requirements while guaranteeing high detection and counting accuracy, which indicates the potential for wheat spikelet counting in highly responsive wheat yield estimation.

Разработка математической модели акустического источника, сопровождающего распад кавитационной каверны на схлопывающиеся пузырьки

Object and purpose of research. This paper is intended to develop a mathematical model of cavitation void fragmentation into separate collapsing bubbles as an acoustic source for further implementation in Logos software package. The study was performed on propeller models in cavitating environment. Subject matter and methods. Volume and quantity of bubbles appearing after fragmentation of a cavitation void on propellers, as well as amplitude and frequency properties of a single bubble collapse are studied as per CFD methods. Viscous flow properties are found from finite-volume (FVM) solution to unsteady Reynolds equations (RANS) closed by a biparametric semi-empirical turbulence model. The coefficients in the mathematical model of acoustic source thus obtained were calibrated through validation that included noise measurements at KSRC Cavitation Tunnel. Main results. This work included numerical simulation of collapse dynamics for a single cavitation bubble at different initial conditions, with approximation of the pressure impact created by bubble collapse in the infinite fluid and near a solid wall. The study estimated volume and quantity of the bubbles created by the fragmentation of cavitation void on propellers (3 propellers of different shape operating at different advance ratios and cavitation numbers). The mathematical model representing above-mentioned process could be further implemented in Logos software as a finite-volume algorithm with k-ω SST turbulence model. The study also created a validation base for further testing and calibration of the mathematical model thus developed. Conclusion. The study was performed as part of project Mathematical simulation on exa- and zetaflops class supercomputers launched by National Centre for Physics and Mathematics (Russia). The analysis of obtained results has shown that the mathematical model suggested in this paper does have practical potential, but it needs additional empirical data for greater flexibility and more accurate estimates. Without this model, these practical tasks still could be handled but at a cost of considerable and, most importantly, unnecessary increase in required hardware resources.

GFRX: A New Lightweight Block Cipher for Resource-Constrained IoT Nodes

The study of lightweight block ciphers has been a “hot topic”. As one of the main structures of block ciphers, the Feistel structure has attracted much attention. However, the traditional Feistel structure cipher changes only half of the plaintext in an iterative round, resulting in slow diffusion. Therefore, more encryption rounds are required to ensure security. To address this issue, a new algorithm, GFRX, is proposed, which combines a generalized Feistel structure and ARX (Addition or AND, Rotation, XOR). The GFRX algorithm uses an ARX structure with different non-linear components to deal with all the branches of a generalized Feistel structure so that it can achieve a better diffusion effect in fewer rounds. The results of a security analysis of the GFRX algorithm show that the effective differential attacks do not exceed 19 rounds and that the effective linear attacks do not exceed 13 rounds. Therefore, the GFRX algorithm has an adequate security level for differential and linear analysis. Avalanche test results obtained for the GFRX algorithm show that the GFRX algorithm has strong diffusion and only takes six rounds to meet the avalanche effect. In addition, the GFRX algorithm can achieve different serialization levels depending on different hardware resource requirements and can achieve full serialization, which ensures operational flexibility in resource-constrained environments.

A Catalog-Based AIG-Rewriting Approach to the Design of Approximate Components

As computational demand and energy efficiency of computer systems are becoming increasingly relevant requirements, traditional design paradigms are bound to become no longer appropriate, as they cannot guarantee significant improvements. The approximate-computing design paradigm has been introduced as a potential candidate to achieve better performances, by relaxing non-critical functional specifications. Anyway, several challenges need to be addressed in order to exploit its potential. In this paper, we propose a systematic and application-independent approximate design approach suitable to combinational logic circuits. Our approach is based on non-trivial local rewriting of and-inverter graphs (AIG), reducing the number of AIG-nodes and possibly resulting in lower hardware resources requirements. We adopt multi-objective optimization to carefully introduce approximation while aiming at optimal trade-offs between error and hardware-requirements. We evaluate our approach using different benchmarks, and, in order to measure actual gains, we perform actual synthesis of Pareto-optimal approximate configurations. Experimental results show that the proposed approach allows achieving significant savings, since resulting approximate circuits exhibit lower requirements and restrained error w.r.t. their exact couterparts.

Interference Mitigation for GNSS Receivers Using FFT Excision Filtering Implemented on an FPGA

GNSS receivers process signals with very low received power levels (&lt;−160 dBW) and, therefore GNSS signals are susceptible to interference. Interference mitigation algorithms have become common in GNSS receiver designs in both professional and mass-market applications to combat both unintentional and intentional (jamming) interference. Interference excision filters using fast Fourier transforms (FFTs) have been proposed in the past as a powerful method of interference mitigation. However, the hardware implementations of this algorithm mostly limited their use to military GNSS receivers where greater power and resources were available. Novel implementation of existing FPGA technology should make interference mitigation feasible with limited hardware resources. This paper details the practicalities of implementing excision filters on currently available FPGAs trading off the achievable performance against the required hardware resources. The hardware implementation of the FFT excision mitigation algorithm is validated with the GNSS software receiver. The results indicate that the desired performance of the developed algorithm has achieved the expectations and can provide significant improvement on mitigation techniques in current GNSS receiver hardware. Two hardware implementation designs (fixed-point and float-point data type format) are developed and compared to achieve the optimal design that can provide the best performance (C/No) with the possible minimum hardware resources.

A lightweight convolutional neural network model with receptive field block for C-shaped root canal detection in mandibular second molars

Rapid and accurate detection of a C-shaped root canal on mandibular second molars can assist dentists in diagnosis and treatment. Oral panoramic radiography is one of the most effective methods of determining the root canal of teeth. There are already some traditional methods based on deep learning to learn the characteristics of C-shaped root canal tooth images. However, previous studies have shown that the accuracy of detecting the C-shaped root canal still needs to be improved. And it is not suitable for implementing these network structures with limited hardware resources. In this paper, a new lightweight convolutional neural network is designed, which combined with receptive field block (RFB) for optimizing feature extraction. In order to optimize the hardware resource requirements of the model, a lightweight, multi-branch, convolutional neural network model was developed in this study. To improve the feature extraction ability of the model for C-shaped root canal tooth images, RFB has been merged with this model. RFB has achieved excellent results in target detection and classification. In the multiscale receptive field block, some small convolution kernels are used to replace the large convolution kernels, which allows the model to extract detailed features and reduce the computational complexity. Finally, the accuracy and area under receiver operating characteristics curve (AUC) values of C-shaped root canals on the image data of our mandibular second molars were 0.9838 and 0.996, respectively. The results show that the deep learning model proposed in this paper is more accurate and has lower computational complexity than many other similar studies. In addition, score-weighted class activation maps (Score-CAM) were generated to localize the internal structure that contributed to the predictions.

Combining Keyframes and Image Classification for Violent Behavior Recognition

Surveillance cameras are increasingly prevalent in public places, and security services urgently need to monitor violence in real time. However, the current violent-behavior-recognition models focus on spatiotemporal feature extraction, which has high hardware resource requirements and can be affected by numerous interference factors, such as background information and camera movement. Our experiments have found that violent and non-violent video frames can be classified by deep-learning models. Therefore, this paper proposes a keyframe-based violent-behavior-recognition scheme. Our scheme considers video frames as independent events and judges violent events based on whether the number of keyframes exceeds a given threshold, which reduces hardware requirements. Moreover, to overcome interference factors, we propose a new training method in which the background-removed and original image pair facilitates feature extraction of deep-learning models and does not add any complexity to the networks. Comprehensive experiments demonstrate that our scheme achieves state-of-the-art performance for the RLVS, Violent Flow, and Hockey Fights datasets, outperforming existing methods.

City Symphony

City Symphony

Research and Implementation of Turbo Coding Technology in High-Speed Underwater Acoustic OFDM Communication

It is demonstrated that the fully parallel turbo decoding algorithm can achieve an approximate error correction decoding performance when 36 iterations are used and when the log-map algorithm with 6 iterations is used. By comparison, it is shown that it can achieve much higher decoding rates than the log-map algorithm for various frame lengths of LTE standard turbo codes at the cost of higher hardware resource requirements. According to the fully parallel turbo decoding algorithm, this paper proposes a scheme for implementing a fully parallel turbo decoder on FPGA, detailing the overall structure and processing of the decoder hardware implementation, the design of the algorithm block processing unit, and the interleaving module. The performance of the decoder is tested by fixed-point simulation for different frame lengths of turbo coding in LTE standard, and it is proved that the fully parallel turbo decoder can be applied to turbo coding of various frame lengths. Both simulation and experimental results show that the distributed cancellation method and the joint estimation cancellation method have good results for both time-domain impulse noise and large-amplitude single frequency noise cancellation, while the joint estimation cancellation method of large-amplitude single frequency noise cancellation first has better performance.

Hardware Platform-Aware Binarized Neural Network Model Optimization

Deep Neural Networks (DNNs) have shown superior accuracy at the expense of high memory and computation requirements. Optimizing DNN models regarding energy and hardware resource requirements is extremely important for applications with resource-constrained embedded environments. Although using binary neural networks (BNNs), one of the recent promising approaches, significantly reduces the design’s complexity, accuracy degradation is inevitable when reducing the precision of parameters and output activations. To balance between implementation cost and accuracy, in addition to proposing specialized hardware accelerators for corresponding specific network models, most recent software binary neural networks have been optimized based on generalized metrics, such as FLOPs or MAC operation requirements. However, with the wide range of hardware available today, independently evaluating software network structures is not good enough to determine the final network model for typical devices. In this paper, an architecture search algorithm based on estimating the hardware performance at the design time is proposed to achieve the best binary neural network models for hardware implementation on target platforms. With the XNOR-net used as a base architecture and target platforms, including Field Programmable Gate Array (FPGA), Graphic Processing Unit (GPU), and Resistive Random Access Memory (RRAM), the proposed algorithm shows its efficiency by giving more accurate estimation for the hardware performance at the design time than FLOPs or MAC operations.