Interference Mitigation for GNSS Receivers Using FFT Excision Filtering Implemented on an FPGA

Abstract

GNSS receivers process signals with very low received power levels (<−160 dBW) and, therefore GNSS signals are susceptible to interference. Interference mitigation algorithms have become common in GNSS receiver designs in both professional and mass-market applications to combat both unintentional and intentional (jamming) interference. Interference excision filters using fast Fourier transforms (FFTs) have been proposed in the past as a powerful method of interference mitigation. However, the hardware implementations of this algorithm mostly limited their use to military GNSS receivers where greater power and resources were available. Novel implementation of existing FPGA technology should make interference mitigation feasible with limited hardware resources. This paper details the practicalities of implementing excision filters on currently available FPGAs trading off the achievable performance against the required hardware resources. The hardware implementation of the FFT excision mitigation algorithm is validated with the GNSS software receiver. The results indicate that the desired performance of the developed algorithm has achieved the expectations and can provide significant improvement on mitigation techniques in current GNSS receiver hardware. Two hardware implementation designs (fixed-point and float-point data type format) are developed and compared to achieve the optimal design that can provide the best performance (C/No) with the possible minimum hardware resources.