Required Hardware Resources Research Articles

A crest factor reduction scheme based on recursive optimum frequency domain matrix

One of the main imperfections in orthogonal frequency division multiplexing (OFDM) techniques is a peak-to-average power ratio (PAPR) or crest factor (CF). High crest factor signal forces a power amplifier in communication systems to back-off which leads to power efficiency degradation. Several techniques have been proposed in literature to mitigate the high peaks in OFDM signal; however most of them suffer from complexity and PAPR performance. In conventional SLM (C-SLM), increasing the number of inverse fast Fourier transform (IFFT) leads to excessive hardware resources requirement and increases system cost. In this paper a novel crest factor scheme based on recursive optimum frequency domain matrix is proposed which requires only two IFFT which results in significant reduction in the computational complexity. Simulation results show both the complexity and crest factor are reduced significantly compared to the conventional methods.

Research on the Construction of Distributed Computer Test System of the Ammunition Warehouse Based on the Grid Technology

Considering to establish a national ammunition warehouse data processing of a large number of real-time monitoring information and real-time transmission to the requirement of server hardware resources, it was proposed to build a national ammunition warehouse distributed test system based on grid technology. Experiments show that the system has a scalable computing capacity, high computational efficiency, low cost, and good application prospect.

Experimental Analysis of the Power Auto-Correlation-Based Chromatic Dispersion Estimation Method

We experimentally investigate the performance of the signal power autocorrelation-based method for chromatic dispersion (CD) estimation in a polarization-multiplexing quadrature phase-shift keying (PM-QPSK) 100G coherent optical system conveying optical channel transport unit level-4 (OTU4) frames. It is shown that the typical laboratory setup, where the signal components are generated from delayed versions of the same pseudorandom binary sequence (PRBS), is inadequate for experimental validation because of artifacts in the signal auto-correlation function. This problem is circumvented by the use of a commercial line card transporting independent data sequences. The algorithm is used to estimate accumulated CD values from 0 to 50 000 ps/nm under up to 80-ps differential group delay (DGD). We further evaluate its convergence properties in terms of the length of the sample vector required for correct CD estimation and address the hardware resource requirements. The CD-shifted version of the algorithm yielded a maximum estimation error of 186 ps/nm in all tested conditions.

Decentralized control for dynamically reconfigurable FPGA systems

The progress in FPGA technology has enabled FPGA-based reconfigurable systems to target increasingly sophisticated applications, which has led to a high control design complexity, resulting in longer design cycles. In this paper, we propose a control design approach for FPGA-based reconfigurable systems aiming at increasing design productivity. This approach is based on a semi-distributed control model that splits different control concerns (monitoring, decision-making and reconfiguration) between autonomous modular controllers and makes use of formalism-oriented design, to decrease the control design complexity and facilitate design verification, reuse and scalability. This model is composed of distributed controllers handling the self-adaptivity of the system reconfigurable regions and a coordinator to respect the system global constraints. To enhance design productivity, the proposed control model is generated automatically using a high-level modeling approach. This approach is based on MDE (Model-Driven Engineering) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard, allowing to make low-level technical details transparent to designers and to automate code generation from high-level models. Experiments on the generated control systems showed that the proposed semi-distributed control model is more flexible, reusable and scalable than the centralized one, at the cost of a slight increase in required hardware resources.

High-speed implementation of rate-distortion optimized quantization for H.264/AVC

Rate-distortion optimized quantization (RDOQ) is generally employed in video coding as an effective tool for pursuing high coding efficiency. Nevertheless, RDOQ requires an exhaustive search over multiple candidates to determine the optimal quantized level by comparing their rate-distortion cost, which leads to considerable complexity in practice. The utilization of inherently strong data dependency and highly sequential process in entropy coding to obtain the information of the bit-rate for each candidate further aggravates the issue of large computational burden. In this paper, a high-speed implementation of RDOQ is proposed to substitute the conventional RDOQ in H.264/AVC. The proposed scheme is low in computational complexity and economical in the requirement of hardware resources. The candidates of quantized levels that are unlikely to be selected are firstly excluded, and then a bit-rate estimation model is constructed for the rest candidates, to avoid the actual entropy coding of context-adaptive binary arithmetic coding for the calculation of the rate-distortion cost. Eventually, the fast algorithm of RDOQ is designed to determine the optimal quantized level, which supports parallel processing and is therefore favorable for hardware implementations. Experimental results demonstrate that the proposed method can decrease the time of RDOQ by 60.5 % in average with a superior RD performance in terms of encoding.

High-throughput CAVLC architecture for real-time H.264 coding using reconfigurable devices

One of the encoding methods offered by H.264 AVC is context-based adaptive variable length coding (CAVLC). This paper presents a high-throughput hardware implementation of the CAVLC encoder. A dual-coefficient scanning phase is investigated and modified to improve the speed of the encoding phase. This improved scanning solution determines all the required data for the encoding phase to be completed in a minimized and constant number of clock cycles. In addition, an algorithmic approach for encoding levels is exploited to reduce hardware resource requirements. The modified scanning phase approach offers significant throughput capabilities for CAVLC: at 200 MHz, the architecture is capable of encoding 1,080 p video files at 95 fps.

Implementation strategy for downgraded flash-memory storage devices

In recent years, low-cost flash-memory devices have contributed greatly to the rapid growth of the flash memory market. Given that the most of the cost of such devices is the cost of the flash-memory chips, many vendors are managing the cost of such devices by using flash-memory chips of low quality, and they will continue to do so in the near future. Recognizing strong market demand, this work presents a set-based mapping strategy with an effective implementation and low hardware resource requirements for making downgraded flash-memory chips useable in products. A configurable management design for managing chips of various qualities with improved lifetime is presented. The effectiveness of the proposed strategy is evaluated by performing a series of experiments and analyzed with reference to popular implementations in industry.

Hardware implementation of new bell-shaped pulse mode neural network with on-chip learning and application to image processing

A key task in the hardware implementation of neural networks is the design of activation functions. We focus in this paper on hardware driven simple implementation of a bell-shaped function BSF avoiding complexity and reducing hardware resources with efficient on-chip learning. This implementation is done in pulse mode to take advantage of its valuable features, significantly reducing the hardware cost. The proposed design is flexible and scalable enabling several image processing potential tasks. A first application is devoted to image denoising where a comparison with some existing denoising techniques demonstrates the efficiency of the proposed approach. As a second application, we consider edge detection operation and good approximation features are accordingly obtained. The corresponding design is implemented on a Virtex-II-PRO FPGA platform. Synthesis results prove that the bell-shaped PMNN is not cumbersome, and provides higher performances versus other PMNN architectures in terms of computing speed and required hardware resources.

A Novel Simulation Fault Injection using Electronic Systems Level Simulation Models

Abstract—In this paper, we propose a novel simulation fault injection method for the dependability analysis of complex SoCs using 32 nm technology. In previous simulation fault injections, the original simulation model is modified to implement a saboteur module or many mutants. This creates a problem since the architectural complexity of current SoCs is expected to increase rapidly in the 32 nm era. Furthermore, the modification process may incur additional tasks, such as verification and validation of the modified simulation model. Our simulation fault injection environment uses the modified SystemC simulation kernel augmented for fault injection experiments. The proposed methodology offers the following advantages over previous simulation fault injection methods. First, it does not require changes in the target simulation design model. Second, it minimizes the simulation hardware resource requirements and simulation time. Third, it allows mixed simulation of the ESL model and the register transfer level model using wrappers. To demonstrate the effectiveness of the proposed methodology, we designed the SystemC models of MIPS and TMR MIPS processors and ran the benchmark SW from MiBench to compare the failure rates of the two processors.

FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5dB for a PER=10−2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested.

MPEG2-TS를 RTP로의 적용 및 변환 시스템

IPTV 콘텐츠는 MPEG2-TS(Moving Picture Expert Group-2 Transport Stream)에 기반을 두고 있으며, 생성된 콘텐츠는 인터넷 서비스망을 이용하여 각 가정의 수신기(Set-Top Box)에 전달되고, 이는 디코딩(Decoding) 과정을 거쳐 텔레비전에 보이게 된다. 하지만 기존의 제공된 회선 이외에 다른 장치에서의 콘텐츠 확대 이용 및 소비는 상당히 제한적 이었으며, 이를 위해 MPEG2-TS를 다른 포맷으로 변환 전송 등의 방법이 다양하게 제공되었으나 이들 방법들은, 시스템에 부하를 많이 가져올 뿐만 아니라, 자체적인 하드웨어 요구 사양이 높아지는 결과를 초래하였다. 이에 본 논문에서는 IPTV 내에서 MPEG2-TS로 제공되는 콘텐츠를 RTP(Real time Transport Protocol)를 이용하여 사용자에게 좀 더 다양한 장치와 환경에 적용 및 제공하는 시스템을 설계 및 구현하였다. 본 논문에서는 기존의 MPEG2-TS로 제공되는 다양한 콘텐츠에 대한 타 장치로의 배포 및 소비가 가능하여 소비자의 콘텐츠 이용에 대한 QoS(Quality of Service)를 향상시킬 뿐만 아니라, 콘텐츠에 대한 소비 및 이용 증가에 따른 IPTV 사업의 발전 및 활성화에 도움이 될 것이다. IPTV contents are based on MPEG2-TS(Moving Picture Expert Group-2 Transport Stream). The Created content is delivered to each home's Set-Top box through the Internet service network, which will be visible on television through the decoding process. The using and spending of content expanding were quite limited in the other existing lines' devices. For this end, provided methods are to convert MPEG2-TS to other format and then transmit it. These methods are causing not only an overload to the system but also its increasing the hardware resource requirements. In this paper, the MPEG2-TS of IPTV's content using RTP(Real time Transport Protocol) provided by the applicable variety of devices and environmental system, was designed and implemented. Through this paper, the existing MPEG2-TS is providing other devices for distribution and consumption that can give better content to the consumers which means that the QoS(Quality of Service) was enhanced. And, the increased consumption and use of content will help the IPTV business to get more development and activation.

Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation

Due to the high computational complexity of discrete cosine transform (DCT) computation, prediction of zero quantized DCT (ZQDCT) coefficients has been extensively studied to reduce the computational complexity of DCT computation. In this letter, we propose a reconfigurable architecture to support ZQDCT computation. Twelve different modes of DCT computations including zonal coding, multiblock processing, and parallel-sequential stage mode can be performed using proposed architecture. We develop a hybrid model-based quality priority algorithm to reduce power consumption, required hardware resources, and computation time with a small quality degradation.

Multi-core based parallel computing technique for content-based image retrieval

In this paper, we propose a parallel computing technique for content-based image retrieval (CBIR) system. This technique is mainly used for single node with multi-core processor, which is different from those based on cluster or network computing architecture. Due to its specific applications (such as medical image processing) and the harsh terms of hardware resource requirement, the CBIR system has been prevented from being widely used. With the increasing volume of the image database, the widespread use of multi-core processors, and the requirement of the retrieval accuracy and speed, we need to achieve a retrieval strategy which is based on multi-core processor to make the retrieval faster and more convenient than before. Experimental results demonstrate that this parallel architecture can significantly improve the performance of retrieval system. In addition, we also propose an efficient parallel technique with the combinations of the cluster and the multi-core techniques, which is supposed to gear to the new trend of the cloud computing.

Chroma Noise Reduction in DCT Domain Using Soft-Thresholding

The chroma noise effect seriously reduces the quality of digital images and videos, especially if they are acquired in low-light conditions. This paper describes the DCT-CNR (Discrete Cosine Transform-Chroma Noise Reduction), an efficient chroma noise reduction algorithm based on soft-thresholding. It reduces the contribution of the DCT coefficients having highest probability to be corrupted by noise and preserves the ones corresponding to the details of the image. Experiments show that the proposed method achieves good results with low computational and hardware resources requirements.

A versatile optoelectronic aid for low vision patients

The purpose of this work is to describe a versatile optoelectronic aid for low vision rehabilitation based on reconfigurable hardware. This aid is easily adaptable to diverse pathologies (with different associated processing tasks) and to the progression of the visual impairment. This platform has a mobile configuration that uses a see-through head-mounted display (Nomad). We have implemented different types of vision enhancement on this versatile platform, and briefly summarize here their computational costs (in terms of hardware resource requirements). We have evaluated two representative capabilities of this aid (Augmented View and digital zoom) with measurements of visual acuity, contrast sensitivity and visual field. We have tested the Nomad head-mounted display and the Augmented View modality, in eight subjects with retinitis pigmentosa: the digital zoom was tested in six low vision subjects and nine normally-sighted subjects. We show that the Nomad display with Augmented View configuration does not impair the residual vision; and that there is an increase in visual acuity (VA) with the digital zoom configuration. The major advantage of this platform is that it can easily embed different image processing tasks and since it is based on a FPGA device, it can be specifically configured to tasks requiring real-time processing.

Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices

Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

1.672 Gigabits/s FPGA based Viterbi decoder for 4D 8PSK TCM

In this paper a novel Viterbi decoder architecture for 4D 8PSK TCM scheme is presented and analyzed. The design includes a new three RAM based traceback unit. With some modification this architecture can be used for different spectral efficiencies of 4D 8PSK TCM schemes as available in the Consultative Committee for the Space Data Systems (CCSDS) standard for the Earth Exploration Satellites (EES). The current design supports data rates up to 1672 MBit/s. Required hardware resources are shown, plus simulation results and measurement from the real-time decoder are discussed.

A novel VLSI architecture for full-search variable block-size motion estimation

Variable block-size motion estimation (VBSME) has become an important technique in H.264/AVC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/AVC based on a full-search motion estimation algorithm. A new scan order is introduced to re-use the sum of absolute differences (SAD) values of smaller sub-blocks on an as-early-as-possible basis, thus the complexity of the required hardware resources, such as registers, multiplexers, and controls is reduced. It also spreads the timing for the final SAD outputs so that the number of output buses is reduced. The architecture is flexible and scalable with regard to the size of the searching windows and PE arrays. Compared to the conventional approaches, the architecture shows higher throughput rate with less hardware. After logic synthesis using DongbuAnam 0.18 mum standard cell library, the number of gates is 39K (16 PEs) in two-input equivalent NAND gates and the maximum operating clock frequency is 416 MHz (256 fps@CIF).

Soft-Computing-Based Embedded Design of an Intelligent Wall/Lane-Following Vehicle

Soft computing techniques are generally well suited for vehicular control systems that are usually modeled by highly nonlinear differential equations and working in unstructured environments. To demonstrate their applicability in real-world applications, two intelligent controllers based on fuzzy logic and artificial neural network are designed for performing a wall-following task. Based on performance and flexibility considerations, the two controllers are implemented onto a reconfigurable hardware platform, namely a field-programmable gate array. As comparative studies of these two embedded hardware controllers designed for the same vehicular application are limited in literature, this research also presents an evaluation of the two controllers, comparing them in terms of hardware resource requirements, operational speeds, and trajectory tracking errors in following different predefined trajectories.

A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors

A cooperative management scheme for power efficient implementations of real-time operating systems on field-programmable gate-array (FPGA)-based soft processors is presented. Dedicated power management hardware peripherals are tightly coupled to a soft processor by utilizing its configurability. These hardware peripherals manage tasks and interrupts in cooperation with the soft processor, while retaining the real-time responsiveness of the operating system. More specifically, the hardware peripherals perform the following power management functionalities: (1) control the on-chip clock distribution network for driving the soft processor, its hardware peripherals, and the bus interfaces between them; (2) perform task and interrupt management responsibilities of the operating system when the soft processor is turned off; and (3) selectively wake up the soft processor and its hardware components, and put them into proper activation states based on the hardware resource requirements of the tasks under execution. The implementations of two popular real-time operating systems on a state-of-the-art FPGA device are presented. Measurements on an experimental board show that the proposed power management scheme can lead to significant power savings.