Replacement Metal Gate Process Research Articles

HfO2-based Ferroelectric Field-Effect-Transistor with Large Memory Window and Good Synaptic Behavior

In this study, the ferroelectric field-effect-transistor (FeFET) with replacement metal gate process was fabricated. The FeFETs with various gate lengths (LG) and gate widths (WG) were investigated, and large average memory window (MW), up to 2.4 V for various LG and WG, was achieved. The influence of LG on MW was investigated. The experimental results show the MW of FeFET increases with decreasing of LG due to fringe effect. Thus, in the design of FeFET, fringe effect must be considered carefully. The influence of annealing temperature on MW of FeFETs was also investigated. The experimental results show that there are similar MW values for various annealing temperatures due to low density of the interface trap. Furthermore, an artificial electronic synapse based on our FeFETs is demonstrated to mimic synaptic response by applying voltage pulses to their gates. FeFET synapse achieves weight update with small nonlinearity (α p = −0.071, α d = −0.095) and asymmetry (∣α p -α d∣ = 0.166). The influence of LG on synaptic properties was also investigated. Artificial neural network (ANN) simulation based on the electronic synaptic arrays using the hand written digits data sets demonstrates a high recognition accuracy of 95.2%, and the influence of LG on recognition accury of ANN was discussed finally.

Investigation of ferroelectric field-effect transistors using a replacement metal gate process

The negative-capacitance field-effect transistor (NCFET) is an emerging steep switching device that utilizes the negative capacitance of the ferroelectric layer to induce voltage amplification in the gate stack. In this study, an NCFET was fabricated by using a replacement metal gate process, which can avoid the influence of high temperature processes on ferroelectric film. The different sub-threshold slope (SS) characteristics of forward gate voltage sweep and reverse gate voltage sweep were investigated. The results show that the different SS characteristics may originate from asymmetrical polarization–voltage (P–V) hysteresis loops of metal–ferroelectric–insulator–silicon capacitance in the NCFET. Moreover, the influences of Hf/Zr ratio, annealing temperature and capacitance size on ferroelectric characteristics were investigated. The experimental results show that there is an optimal Hf/Zr ratio and annealing temperature that maximizes the residual polarization (P r). For ferroelectric field-effect transistor (FeFET) memory design, the largest P r should be chosen to increase retention time. For ferroelectric NCFET logic design, the negative capacitance can be adjusted by changing the Hf/Zr ratio and annealing temperature to achieve better capacitance matching between positive capacitance and negative capacitance. It is expected that experimental results may provide some guidance for the design and performance enhancement of FeFETs and NCFETs.

Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process

In this work, the influences of zero-level interlayer dielectric (ILD0) materials on the fabrication of silicon nanowire (SiNW) gate-all-around (GAA) transistors based on conventional mainstream FinFET replacement metal gate (RMG) technology were investigated. We find that the fins in the source/drain (SD) regions covered by conventional plasma-enhanced chemical vapor deposition (PECVD) of SiO2 are seriously eroded after NW release and surface processing. To achieve desirable device fabrication, new fabrication technologies with ILD0 materials formed by PECVD SiNx and low pressure chemical vapor deposition (LPCVD) SiNx are introduced to replace the conventional PECVD SiO2. The results demonstrate that the PECVD SiNx ILD0 device overcomes the eroding issue at SD in NW release process but causes spacers exfoliation. In contrast, the LPCVD SiNx ILD0 provides excellent preservation of the SD fins as well as the adjacent spacers. Fully isolated SiNW GAA transistors with the LPCVD SiNx ILD0 film are successfully fabricated with well electrical characteristics and higher yield. The proposed optimized approach provides a robust processing window for the fabrication of GAA NW transistors.

(Keynote) Gate-All-Around Nanowire & Nanosheet FETs for Advanced, Ultra-Scaled Technologies

As two-dimensional CMOS scaling is reaching its physical limits, maintaining profitable node-to-node cost-per-transistor gains requires increasingly constraining design restrictions. To help preserve the power, performance, area, and cost (PPAC) logic roadmap several innovations are being explored, such as cell height reduction by decreasing the number of metal tracks. This allows compensating for the recent trend of a more modest pitch scaling, but it also requires fin depopulation from two fins to one fin per finFET transistor for ultra-scaled cells with reduced number of metal tracks [1,2], which impacts the device performance. As such, in order to keep the scaling gains, introduction of novel device architectures is needed, with gate-all-around (GAA) nanowire (NW) or nanosheet (NS) FETs [2-8] being regarded as the most promising finFET replacements for advanced nodes (Fig. 1). These devices provide better electrostatics allowing further gate length (Lgate) scaling, with NS offering higher current drivability (ION) per layout footprint than NW thanks to larger effective widths (Weff). Furthermore, by having the option to vary the NS Weff on the same chip/wafer, this enables additional design flexibility, typically targeting wider NS for high performance computing and narrower NS for low power applications [5,7,8]. At the same time, vertically stacking several NS enables further boosting ION at the expense of an increase in parasitic capacitance. Minimizing the latter is crucial for delivering both optimal performance and power efficiency. That can be achieved by reducing the vertical distance between the stacked lateral NS as demonstrated in Fig. 2 and via the implementation of inner spacers in-between them [2,6]. Both features introduce considerable challenges for device fabrication. However, it still shares many of the building blocks of a finFET flow thus allowing a smoother technological transition for manufacturing as compared to other device architectures. In the case of the NS vertical pitch, its shrinkage requires scaled Si/SiGe-multilayer stacks growth and thinner gate stacks that can be implemented with the guarantee of similar gate control on all NS surfaces. That has been demonstrated for a stack with an alternative, thinner (<2.5nm) n-type effective work function (EWF) metal layer yielding tight, low threshold voltage values (VT < 0.2V - NMOS), while showing improved noise and reliability behavior [9].Another GAA device architecture, with vertical NW or NS (VNW/VNS) and vertically defined Lgate, has been shown to have the potential to enable denser and more energy efficient SRAMs and MRAMs when used as the cell transistors or selector, respectively [10-13]. In the overall scaling roadmap, the latter type of memory has been gaining increased momentum as an alternative for enabling large, ultra-high-density last-level caches for systems with reduced area and energy. Overall, GAA VNW/VNS FETs represent a more disruptive technological transition, moving from 2D to 3D layouts. Nevertheless, they can also open new scaling paths in the third dimension. In this context, the feasibility of co-integrating on the same wafer and in a cost-effective way finFETs (or GAA lateral NS FETs) for high performance logic and GAA VNS FETs as MRAM selector is evaluated by process simulations, experimentally validated for each type of devices (Fig. 3). In this scheme, cost adders were minimized by sharing the maximum number of critical process steps for both FETs. A replacement metal gate process, standardly used in finFETs and lateral NS FETs can be also advantageous for VNS FETs as it can allow shrinkage of the channel cross-section for improved electrostatics (without impacting the bottom/top S/D [14]), while also enabling new techniques for stress-induced mobility enhancement [12]. Specific for VNS FETs, a self-aligned gate electrode can be easily implemented by relying on the different oxidation kinetics of Si and SiGe and using SiGe/Si/SiGe instead of Si-only pillars.

Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process

In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- k /metal gate FinFET flow are implemented to fabricate the GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H2 baking and oxidation methods in the RMG process. The proposed methods would increase the process thermal budget and improve film quality for the NW channels. Providing both structural and process advantages, the optimized devices with $L_{g} = 16$ nm demonstrate superb short-channel effect (SCE) immunity characteristics, with SS = 61.86$ mV/dec and DIBL = 6.5 mV/V for the inverted droplet NW device; these results are very close to the ideal limits of MOSFETs. The results also indicate that the inverted droplet NW devices have a slightly better SCE control than the circular NWs of similar geometric size.

DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration

We report the first RF characterization of short-channel replacement metal gate (RMG) InGaAs-OI nFETs built in a 3D monolithic (3DM) CMOS process. This process features RMG InGaAs-OI nFET top layer and SiGe-OI fin pFET bottom layer. We demonstrate state-of-the-art device integration on both levels. The bottom layer SiGe-OI pFETs are fabricated with a Gate-First (GF) process with fins and featuring epitaxial raised source drain (RSD) as well as silicide contact layer. The top layer InGaAs nFETs are fabricated with a RMG process featuring a self-aligned epitaxial raised source drain (RSD). We show that the 3D monolithic integration scheme does not degrade the performance of the bottom SiGe-OI pFETs owing to an optimized thermal budget for the top InGaAs nFETs. From the RF characterizations performed (post-3D monolithic process) on multifinger-gate InGaAs-OI nFETs, we extract a cut-off frequency (Ft) of 16.4GHz at a gate-length (Lg) of 120nm. Measurements on various gate lengths shows increasing cut-off frequency with decreasing gate-length.

(Invited) A Brief History of Selective Epitaxy (at IBM SRDC)

Over more than a decade—and half a dozen technology nodes—selective expitaxy has consistently been a major performance element, propelling logic devices to their ultimate targets. Throughout this period (the “Epi Renaissance”), a huge variety of epitaxial processes have been evaluated across the semiconductor industry. Because each technology generation has unique constraints and process assumptions, these epitaxy processes have varied significantly in shape, size, and composition. And of course not all survived to be implemented in full production. This presentation gives a retrospective survey of each of these epitaxial processes, ranging from a simple, single undoped Si raised source/drain to multi-pass growth with complex multi-layer film stack. Selective epitaxy at IBM SRDC began with an undoped selective Si raised source drain (RSD) at the 90nm technology node, used to improve the silicide formation and placement. This was a key enabling feature of the Si on SiGe on insulator (SGOI) technology [1]. Since the silicide had difficulties with the SiGe underlayer, a selective epitaxial Si solution allowed significantly improved contact resistance. SGOI showed great promise on long channel devices, and due to the uniaxial nature of the strain it showed a clear performance benefit on both NFET and PFET. Unfortunately, the short channel devices were consistently degraded, so for the ultimate performance targets IBM instead turned to stressed nitride liners to deliver channel strain [2], while Intel introduced embedded SiGe source/drain (eSiGe) [3]. IBM incorporated eSiGe as a PFET performance element starting at the 65 nm node. However, instead of an in-situ boron doped eSiGe grown just prior to silicide (late eSiGe) similar to what Intel had published, IBM used a lower %Ge, undoped SiGe film grown just after gate module (early eSiGe). Early eSiGe was effectively a “drop-in” solution that allowed for minimal disruption to the existing integration and device design while still providing significant performance gains via channel strain [4]. For the 45nm node IBM published a novel method called Hybrid Orientation Substrate (HOT) that enabled PFET performance gain by changing the PFET Si crystal orientation from <100> to <110>. This method utilized a SOI wafer with <100> top Si layer bonded to a <110> handle wafer. At the beginning of the process, the PFET regions were etched down through the buried oxide, and a thick, undoped selective Si epi was then re-grown on the <110> substrate. In contrast to SGOI the benefit of HOT was demonstrated even on short channel devices. Even better, this mobility increase was shown to be additive with eSiGe strain [5]. Unfortunately a combination of factors including significantly higher substrate cost, area density penalty from expanded groundrules, and concerns about defectivity of the selective epitaxial re-growth prevented it from being implemented in full manufacturing. Instead of HOT, a second generation early eSiGe process was developed with closer proximity to the gate, and increased recess depth [6]. At the 32nm node IBM was focused on the switch to high-K with metal gate, and again IBM and Intel’s solutions diverged. IBM and partner companies used a “gate first” integration flow, contrasted with Intel’s “gate last” replacement metal gate process. Since differential metal workfunction tuning was unavailable in the gate-first integration, IBM introduced a second epitaxy step, growing a thin layer of channel SiGe on the PFET in order to separately tune the PFET threshold voltage [7], and increase performance [8]. Despite remaining planar and gate first, 22nm saw multiple disruptive changes in the source/drain epi module. IBM gained an industry first with the introduction of strained Si:CP in the NFET S/D, a process that required cyclic dep/etch in order to achieve high substitutional carbon incorporation [9]. On the PFET side, the reduced dimensions and the effect of ion implant lateral straggle finally forced a switch from early to late eSiGe. This change drove increased complexity in the epi by adding a buffer layer to control dopant out-diffusion, a ramped high-boron main layer, and a cap layer for improved silicide. Additionally, both NFET and PFET benefited from the introduction of an integrated preclean module, where the wafer does not break vacuum in between oxide etch and epitaxial growth. Today, the 14nm node marks the arrival of FinFETs at the SRDC – with significant integration differences compared to Intel’s FinFET solution. IBM chose to stay with SOI substrate, leading to challenges with the source/drain recess for embedded SiGe. Eventually, IBM sidestepped the recess issue by implementing cladded epitaxy for both the PFET and NFET source/drain, focusing on improving performance by lowering contact resistance instead of straining the channel [10]. Figure 1

Defectivity control of aluminum chemical mechanical planarization in replacement metal gate process of MOSFET**Project supported by the Major National Science and Technology Special Projects (No. 2009ZX02308), the Natural Science Foundation for the Youth of Hebei Province (Nos. F2012202094, F2015202267), and the Outstanding Youth Science and Technology Innovation Fund of Hebei University of Technology (No. 2013010).

The replacement metal gate (RMG) defectivity performance control is very challenging in high-k metal gate (HKMG) chemical mechanical polishing (CMP). In this study, three major defect types, including fall-on particles, micro-scratch and corrosion have been investigated. The research studied the effects of polishing pad, pressure, rotating speed, flow rate and post-CMP cleaning on the three kinds of defect, which finally eliminated the defects and achieved good surface morphology. This study will provide an important reference value for the future research of aluminum metal gate CMP.

Metal Flake Defect and Its Formation Mechanism during Replacement Metal Gate CMP Process

Replacement metal gate (RMG) has been introduced in semiconductor fabrication since 45 nm gate scaling era. RMG process has advantages in prevention of damage by gate etch and thermal process, and it gives work function material stability. Moreover, improvement of device performance is expected as well. Therefore it has been employed as industry standard process for advanced node transistor fabrication. However, the complexity of RMG process flow emphasizes the importance of metal gate chemical mechanical polishing (CMP) which plays a key role in the success of RMG formation. Three complementary CMP steps (gate poly-Si CMP, poly-Si open CMP, metal gate CMP) are involved in RMG formation and comprehensive understanding of interplay among these CMP steps is the key to achieve uniform gate height across the wafer. In addition to extremely tight control of final gate height, post metal gate CMP defects are one of the most critical parameters affecting device performance as well as yield. Among various kinds of defects, metal flakes are most serious defect which fails transistor function by providing gate leakage channel. This paper approaches both integrational and CMP process aspect to reveal the mechanism of metal flake formation.

Ni(Pt) silicide with improved thermal stability for application in DRAM periphery and replacement metal gate devices

In comparison to standard CMOS devices for logic applications, periphery devices for DRAMs typically require a long anneal in the temperature range between 600 and 800°C after the silicide formation. This gives additional constraints in many process steps, in particular in the silicidation step. In this work the feasibility and optimization of a thermally stable NiPt silicide has been investigated. First, a blanket wafer study has been done showing that a thermally stable silicide (TSS) can be obtained by using a pre-amorphization implant (PAI)+C implant+laser anneal prior to the silicidation process, and a superior thermal stability can be obtained using a spike anneal rather than a laser anneal. Then, this silicide was successfully integrated in low voltage CMOS HKMG devices (Lgate down to 32nm) without affecting the junction behavior, and featuring only minor effects on devices performance compared to a non-stabilized NiPt silicide without DRAM anneal, with applicability in a replacement metal gate process flow.

Dummy Oxide Removal in High-K Last Process Integration how to Avoid Silicon Corrosion Issue

The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).

Aluminum Alloy Formation and Impacts in Advanced Replacement Metal Gate Process

ABSTRACTFor the gate last approach of a high K metal gate scheme used in advanced CMOS technology, various materials were tested as wetting layers to allow Aluminum (Al) gap fill at gate widths of10 to 45 nanometers. In this study, Titanium (Ti) and Cobalt (Co) were investigated as a wetting layer for Al gap fill. It was discovered that Al-Ti and Al-Co alloys were formed during high temperature Al deposition. Alloys were characterized using XRD. Alloy’s impacts on line resistivity and subsequent Al Chemical Mechanical Polish (Al CMP) were also investigated. In addition, a model was established to predict the alloy type and alloy mole% with respect to feature size. The predicted Al mole% by this model correlated very well with 1) line resistivity trend and 2) morphologies. The model also predicted that due to Al lower electro-chemical potential than Ti, Co or its alloys, galvanic corrosion could take place depending on the chemical environment in the Al CMP slurry. Different slurry or cleaning chemical may reduce or increase the risk of galvanic corrosion. The knowledge gained with the help of the model provides clear directions on selection criteria for wetting layers, optimization for deposition processes and Al CMP consumable design to meet the challenges.

Evaluation of MOSFETs with crystalline high-k gate-dielectrics: device simulation and experimental data

The evaluation of the world’s first MOSFETs with epitaxially-grown rare-earth high-k gate dielectrics is the main issue of this work. Electrical device characterization has been performed on MOSFETs with high-k gate oxides as well as their reference counterparts with silicon dioxide gate dielectric. In addition, by means of technology simulation with TSUPREM4, models of these devices are established. Current-voltage characteristics and parameter extraction on the simulated structures is conducted with the device simulator MEDICI. Measured and simulated device characteristics are presented and the impact of interface state and fixed charge densities is discussed. Device parameters of high-k devices fabricated with standard poly-silicon gate and replacement metal gate process are compared.

Effect of CF/sub 4/ plasma pretreatment on low temperature oxides

This study describes a novel technique for forming low temperature oxides (<350/spl deg/C) using a replacement metal gate process. Low temperature oxides were generated by N/sub 2/O plasma in a PECVD system with pretreatment in CF/sub 4/. Fabricated oxides demonstrate excellent current-voltage (I-V) characteristics, such as low leakage current, high breakdown charge and good reliability. Experimental results indicate that CF/sub 4/ plasma treatment can significantly improve the mobility and resistance against hot carrier stress of MOSFETs. With excellent electrical properties, this technique is suitable for fabrication low temperature devices.