Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process

Abstract

In this work, the influences of zero-level interlayer dielectric (ILD0) materials on the fabrication of silicon nanowire (SiNW) gate-all-around (GAA) transistors based on conventional mainstream FinFET replacement metal gate (RMG) technology were investigated. We find that the fins in the source/drain (SD) regions covered by conventional plasma-enhanced chemical vapor deposition (PECVD) of SiO2 are seriously eroded after NW release and surface processing. To achieve desirable device fabrication, new fabrication technologies with ILD0 materials formed by PECVD SiNx and low pressure chemical vapor deposition (LPCVD) SiNx are introduced to replace the conventional PECVD SiO2. The results demonstrate that the PECVD SiNx ILD0 device overcomes the eroding issue at SD in NW release process but causes spacers exfoliation. In contrast, the LPCVD SiNx ILD0 provides excellent preservation of the SD fins as well as the adjacent spacers. Fully isolated SiNW GAA transistors with the LPCVD SiNx ILD0 film are successfully fabricated with well electrical characteristics and higher yield. The proposed optimized approach provides a robust processing window for the fabrication of GAA NW transistors.