IC Reliability Research Articles

IC Packaging Material Identification via a Hybrid Deep Learning Framework with CNN-Transformer Bidirectional Interaction.

With the advancement of micro- and nanomanufacturing technologies, electronic components and chips are increasingly being miniaturized. To automatically identify their packaging materials for ensuring the reliability of ICs, a hybrid deep learning framework termed as CNN-transformer interaction (CTI) model is designed on IC packaging images in this paper, in which several cascaded CTI blocks are designed to bidirectionally capture local and global features from the IC packaging image. Each CTI block involves a CNN branch with two designed convolutional neural networks (CNNs) for CNN local features and a transformer branch with two transformers for transformer global features and transformer local-window features. A bidirectional interaction mechanism is designed to interactively transfer the features in channel and spatial dimensions between the CNNs and transformers. Experimental results indicate that the hybrid framework can recognize three types of IC packaging materials with a good performance of 96.16% F1-score and 97.92% accuracy, which is superior to some existing deep learning methods.

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

Artificial intelligence deep learning for 3D IC reliability prediction

Three-dimensional integrated circuit (3D IC) technologies have been receiving much attention recently due to the near-ending of Moore’s law of minimization in 2D IC. However, the reliability of 3D IC, which is greatly influenced by voids and failure in interconnects during the fabrication processes, typically requires slow testing and relies on human’s judgement. Thus, the growing demand for 3D IC has generated considerable attention on the importance of reliability analysis and failure prediction. This research conducts 3D X-ray tomographic images combining with AI deep learning based on a convolutional neural network (CNN) for non-destructive analysis of solder interconnects. By training the AI machine using a reliable database of collected images, the AI can quickly detect and predict the interconnect operational faults of solder joints with an accuracy of up to 89.9% based on non-destructive 3D X-ray tomographic images. The important features which determine the “Good” or “Failure” condition for a reflowed microbump, such as area loss percentage at the middle cross-section, are also revealed.

Fault Coexistence and Grading Aware TSV Test based on Delay Feature

Screening out the defects in the TSV manufacturing process and eliminating the resistive open fault and leakage fault as early as possible are beneficial to improve the yield and reliability of 3D ICs. The existing prebond test methods are confined to the test accuracy and de- tection range, especially the test confusion prob- lem and the lack of diagnosable ability under the coexistence of multiple faults. Based on the uc- tuation of delay feature caused by faults, a kind of fault coexistence and grading aware TSV test method is proposed to enhance the yield and reli- ability of TSVs in this paper. The reference TSV and the TSV under test are input with test stim- uli simultaneously. Furthermore, the designed delay extraction circuit is utilized to generate the rising edge and the falling edge separately and additional fault grading circuit can be enriched according to the test requirements. Finally, a one bit comparator at the capture end is used to detect whether two pulse signals arrive simul- taneously, so as to determine whether there is a fault and the type of fault. The simulation results indicate that the detection range of resistive open fault is more than 281 , and the detection range of leakage fault is less than 223 M , which is bet- ter than most existing methods. While effective- ly solving resistive open fault and leakage fault, it can also successfully deal with the coexistence of two kinds of faults and achieve a 5-level fault grading ability with relatively low area overhead.

Scoring Endoscopy in Pediatric Inflammatory Bowel Disease

There are a large interobserver variability in evaluating mucosal lesions of inflammatory bowel disease (IBD), especially in pediatric patients. This multicenter prospective observational study aims to evaluate interobserver agreement (IOA) among pediatric endoscopists in assigning validated IBD endoscopic scores in children. Fifteen videos of follow-up ileocolonoscopies in children with IBD were recorded and selected as cases. Eleven pediatric endoscopists from different centers blindly evaluated all videos and calculated scores: either Ulcerative Colitis Endoscopic Index of Severity (UCEIS) or simple endoscopic score for Crohn's Disease (SES-CD). Scores from all reviewer were compared in order to calculate IOA for general videos and specific sections. Scores from an expert adult reader were used to calculate possible reviewer's characteristics affecting scores reliability. Intraclass correlation was 0.298 (95% CI: 0.13-0.55) for UC and 0.266 (0.11-0.52) for CD. When a disease activity categorization was adopted (remission, mild, moderate, severe activity) Fleiss' kappa coefficient was 0.408 (0.29-0.53) for UC and 0.552 (0.43-0.73) for CD. When stratified by item, vascular pattern of UC was the most reliable item IC: 0.624 (0.321-0.854). In multivariable analysis none of the reviewer's characteristics affected the readers' errors. This multicenter study shows low agreement among pediatric endoscopists in evaluating endoscopic scores in children with IBD. By using disease activity categorization, agreement slightly increased, mostly for CD. All readers showed a low-grade concordance with the expert adult gastroenterologist's evaluations. Future specific training programs should be considered to increase interobserver agreement in using IBD endoscopic activity scores.

AI-Powered Terahertz VLSI Testing Technology for Ensuring Hardware Security and Reliability

Hardware cybersecurity has become a key issue, especially for very large integrated circuits. If counterfeit, forged, or defective ICs present a significant threat to system reliability and security. The growing complexity of digital and mixed-signal systems makes it increasingly challenging yet vital to develop robust methods to assess and confirm the reliability and authenticity of ICs. We introduce a new terahertz testing method for non-destructive and unobtrusive identification of counterfeit, damaged, forged or defective ICs by measuring their response to incident terahertz and sub-terahertz radiation at the circuit pins and analyzing the response using artificial intelligence (AI). These responses create unique signatures for ICs. We generated 2D images by measuring the response on a selected pin of a radio frequency IC (RFIC) scanned by a focused terahertz radiation. By applying the data augmentation processes, we created a secure image data set to train the convolutional neural network (CNN) model. An unsecured image data set representing altered or damaged ICs was generated by modifying the original image data. The trained models identified secure devices with a ~94% accuracy.

Estimation of the independent components reliability of EEG signal in a clinical application

Independent Component Analysis (ICA) is a statistical method that has effective roles in processing the electroencephalography (EEG) signal, especially for finding artifacts. This research aimed to automatically estimate the validity of independent components in the EEG signal and extracting more brain-related sources. Data were obtained from adult attention deficit hyperactivity disorder (ADHD) participants and control groups during the continuous performance task (CPT). The reliability of ICs was estimated by different methods, including the statistical validity measurement for each component, their physiological plausibility and the equivalent dipole interpretation both in time and frequency domain. Group-ICA algorithm was applied to ADHD/control groups in order to compare the validity of components between subjects. Homogenous components in each group were determined by clustering. The results showed that in all algorithms, including the automatic algorithm and Group-ICA, the number of reliable components in the frequency domain is greater than (about twice) the number of estimated components in the time domain. Statistical results (Wilcoxon signed-rank test) for comparison the number of reliable components of degree 3 in both methods showed a significant difference (P-value: 0.0113) and the same result was observed for reliable components of degree 2 (P-value: 4.8e-04).

Detection and Diagnosis of Multi-Fault for through Silicon Vias in 3D IC

Through silicon via (TSV) is the enabling technology for three-dimensional integrated circuit (3D IC) realization. During the TSV manufacturing process, the TSV inevitably has a multi-fault with both resistive-open and leakage faults. The multi-fault will decrease the reliability of the 3D IC seriously. A method of classifying and diagnosing TSV multi-fault is proposed by combining ring oscillator and least square support vector machine (LSSVM). Firstly, the schmidt trigger (ST) as a TSV test receiver based on the initial ring oscillator test structure is implemented. The parameters such as the oscillation period and duty cycle are measured with the TSV as load. A variety of fault types can be detected by testing the changes of these parameters. For further increase the accuracy of the fault test, the oscillation period and duty cycle of different faults are utilized as the feature vectors set, and the set is trained by LSSVM to obtain the fault diagnosis model. In order to get the optimization parameters of the LSSVM model, the particle swarm optimization (PSO) is adopted. As the problem of PSO is tend to local optimization and premature convergence, it may lead to misjudgment of TSV fault. Based on this, W-PSO that dynamically changes the inertia weight is used to optimize the LSSVM. Finally, experiment results imply that the W-PSO-LSSVM fault diagnosis model has a higher fault diagnosis accuracy rate than the PSO-LSSVM fault diagnosis model.

A self-adaptive pulse generator to realize extremely low power consumption and high reliability of high voltage gate driver IC

A self-adaptive pulse generator featuring with short pulse width to realize lower power consumption and higher reliability of high voltage gate driver IC is proposed. Under the control of the feedback signal from the output of the high voltage level shifter, the pulse width of the input narrow pulse can be decreased adaptively without affecting the normal operating function. The proposed self-adaptive pulse generator is implemented in 100 V BCD process. Measured results show that the pulse width reduced from 211.6 to 108.3 ns, the high side operating current decreased from 175.54 to 120.53 µA at 25 °C when operations at 100 kHz, and the pulse width tend to be stable as temperature changes.

P141 Scoring endoscopy in pediatric inflammatory bowel disease: a way to improve quality

Abstract Background The aim of mucosal healing (MH) as a therapeutic target in paediatric inflammatory bowel diseases (IBD) has emphasised the role of the endoscopy. There is a great variability in evaluating mucosal lesions among different operators, especially in paediatric patients. This multicentre prospective study aims to evaluate the interobserver agreement among paediatric endoscopists in using validated endoscopic scores of IBD in children. Methods Fifteen videos of follow-up ileocolonoscopies in children with IBD (8 ulcerative colitis –UC-, 7 Crohn’s disease –CD-) were selected from 3 different referral sites in Italy. Eleven paediatric endoscopists from different centres were asked to evaluate all videos as independent and blinded readers. The scoring systems used were ulcerative colitis Endoscopic Index of Severity (UCEIS) for UC and simple endoscopic score for Crohn’s disease (SES-CD) for CD. Kappa statistics and intraclass correlation coefficients were used to measure agreement. Furthermore, an experienced adult gastroenterologist evaluated the same videos and scores them. His results were compared with paediatric endoscopists’ findings. Results The median age of the participants was 40 (interquartile range: 6) with a median experience of 12 (14) years in centres with a median number of 140 (230) of paediatric IBDs. Intercluster correlation agreement was 0.298 (95% CI: 0.13–0.55) for UC and 0.266 (0.11–0.52) for CD. When a disease activity categorisation was adopted (remission, moderate, mild and severe) Fleiss’ kappa coefficient was 0.408 (0.29–0.53) for UC and 0.552 (0.43–0.73) for CD (Figure 1). When stratified for item vascular pattern of UC was the most reliable item IC: 0.624 (0.321–0.854). The comparison between paediatric and expert gastroenterologist’s scores is shown in Figure 2. In the multivariate analysis none of the reviewer characteristic affected the readers’ errors. Conclusion This pilot multicentre study shows that there is a low level of agreement among paediatric endoscopists in evaluating children with IBDs. Agreement improved after using a disease activity categorisation, with better results for CD. Regardless to experience, all readers showed a low-grade accordance with adult gastroenterologist. According to these findings, the use of scoring systems should be implemented for all paediatric endoscopists. Future specific training programs should be considered to pursue this goal.

NBTI and HCI Aging Prediction and Reliability Screening During Production Test

With the semiconductor manufacturing technology approaching to 14 nm and below, the reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging mechanisms, including negative bias temperature instability (NBTI) and hot carrier injection (HCI). Furthermore, significant process variations differ the aging degradation rate of each individual IC, which causes significant failure time differences even for the ICs belonging to the same lot. Therefore, to select devices for the applications with various reliability requirements, it is necessary to conduct efficient predictive reliability screening during production test at time-zero. In this article, a fast time-zero aging prediction and predictive screening methodology based on a novel on-chip architecture named ZeroScreen is proposed. The pattern-based aging screening time is limited to 8.14 ms per device considering 50-MHz test clock frequency and 6.6- $\mu \text{s}$ automatic test equipment (ATE) voltage settling time. In the experiment, fresh 45-nm FPGA devices and 130-nm ASIC chips are projected into four reliability bins with ZeroScreen-based aging prediction at time-zero. According to the silicon data, the reliability screening errors of ZeroScreen for the 45-nm FPGA chips are less than 6.5% and 4.3% for static and dynamic stress cases, respectively. And the screening errors for the 130 nm ASIC chips are close to 0, for both static and dynamic stress cases.

Runtime Stress Estimation for Three-dimensional IC Reliability Management Using Artificial Neural Network

Heat dissipation and the related thermal-mechanical stress problems are the major obstacles in the development of the three-dimensional integrated circuit (3D IC). Reliability management techniques can be used to alleviate such problems and enhance the reliability of 3D IC. However, it is difficult to obtain the time-varying stress information at runtime, which limits the effectiveness of the reliability management. In this article, we propose a fast stress estimation method for runtime reliability management using artificial neural network (ANN). The new method builds ANN-based stress model by training offline using temperature and stress data. The ANN stress model is then used to estimate the important stress information, such as the maximum stress around each TSV, for reliability management at runtime. Since there are a variety of potential ANN structures to choose from for the ANN stress model, we analyze and test three ANN-based stress models with three major types of ANNs in this work: the normal ANN-based stress model, the ANN stress model with hand-crafted feature extraction, and the convolutional neural network–(CNN) based stress model. The structures of each ANN stress model and the functions of these structures in 3D IC stress estimation are demonstrated and explained. The new runtime stress estimation method is tested using the three ANN stress models with different layer configurations. Experiments show that the new method is able to estimate important stress information at extremely fast speed with good accuracy for runtime 3D IC reliability enhancement. Although all three ANN stress models show acceptable capabilities in runtime stress estimation, the CNN-based stress model achieves the best performance considering both stress estimation accuracy and computing overhead. Comparison with traditional method reveals that the new ANN-based stress estimation method is much more accurate with a slightly larger but still very small computing overhead.

STREAM: Stress and Thermal Aware Reliability Management for 3-D ICs

Accurate and fast reliability management is important for 3-D integrated circuits (3-D ICs) because of the severe on-chip thermal and reliability problems. However, due to the lack of stress information and difficulties in implementing management method for reliability, existing full-chip reliability management methods suffer from low management accuracy and high system performance degradation. In this paper, we propose a new stress and thermal aware reliability management method for 3-D ICs called STREAM. Unlike traditional methods which do not perform explicit stress analysis due to the large computing cost, STREAM employs an artificial neural network-based stress model to estimate stress accurately at runtime. In order to further improve the reliability management accuracy and improve the system performance, a lifetime estimator with lifetime banking technology and a specially designed lifetime model predictive control are integrated into the reliability management framework. Our numerical results show that STREAM performs the stress and thermal aware full-chip reliability management with both high accuracy and speed. It is able to boost the performance of 3-D ICs and outperforms the state-of-the-art 3-D IC reliability management method.

Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing

Three-dimensional Integrated Circuits (3D ICs) based on Through-Silicon Vias (TSVs) provide many benefits, such as high density, high bandwidth and low-power consumption. However, defects in TSV due to complex fabrication steps decrease the yield and reliability of 3D ICs. Therefore each die should be tested before it is stacked through pre-bond test. Pre-bond test and defect identification of TSVs are extremely important to screen out defective TSVs early in the manufacturing flow. Also, test cost minimization is one of the key issues of the testing process. The existing test time minimization solutions for pre-bond test consider random TSV defects. However, in practice clustered TSV faults are quite common. In this paper, we propose a novel test time minimization technique to address both random and clustered defect distributions. The proposed solutions are based on recursive bi-partitioning and padding of test sessions to minimize the number of required test sessions as well as test time. Simulation results show that the proposed method can achieve more than 50% reduction in test time for a 20-TSV network with four faulty TSVs compared to serial testing approach. The proposed algorithm also pinpoints the defective TSVs in a TSV network with a reduced test time compared to prior works.

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method

Thermomechanical stress is one of the most important issues in performance and reliability analysis of through silicon via-based 3-D integrated circuits (3-D ICs), where an accurate numerical approach is generally needed to produce stress models and identify weak points in the structure. In this paper, we propose a knowledge-oriented nonuniform (KONU) refinement strategy for 3-D IC stress simulation under the framework of a parallel adaptive finite element method (FEM), and apply it in 3-D IC stress and reliability analysis. Parallel adaptive FEM is promising for solving large-scale problems due to its high accuracy and parallel efficiency. It produces refined meshes based on the a posteriori error analysis, which has the quasi-optimal convergence rate for solving the problem. It has high parallel efficiency, which makes it suitable for handling large and complex structures in 3-D ICs. The KONU refinement strategy developed in this paper can efficiently reduce the number of refinement iterations in parallel adaptive FEM for 3-D IC thermomechanical stress simulation and improves the computational efficiency. It is demonstrated in this paper through several examples that parallel adaptive FEM for thermomechanical stress evaluation can be widely applied in 3-D IC reliability analysis, where accurate stress simulation and modeling is exceptionally important to produce accurate results.

A Predictive Model for IC Self-Heating Based on Effective Medium and Image Charge Theories and Its Implications for Interconnect and Transistor Reliability

Spatially resolved precise prediction of local temperature ${T}(\textit {x,y,z})$ is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling (FEM) do provide excellent results, but the calculation is too time-consuming for a structure that involves eight to ten layers of percolating interconnects, especially for fast turn-around reliability modeling. Here, an analytical model that can quickly/accurately determine $\textit {T(x,y,z)}$ will reduce the design time of self-heated modern IC. In this paper, we 1) develop a physics-based electrothermal compact model for ICs to predict $\textit {T(x,y,z)}$ based on the synthesis of effective medium theory, image charge theory, and Rent’s rule; 2) validate our model against 3-D FEM and experimental data; and 3) predict back-end-of-line (BEOL) reliability (i.e., electromigration at each layer) based on the temperature profile. Since our analytical model predicts changes in $\textit {T(x,y,z)}$ with any given IC’s configuration (e.g., interconnect wire length and number distribution, metal volume fraction in BEOL, heat sinks mechanisms, materials, and type of devices), it suggests new opportunities for optimization of performance and reliability of modern ICs.

A thermal protection module for automotive integrated circuits

Automotive ICs work in wide ambient temperature range up to 150[Formula: see text]C. It is important to design an over temperature protection mechanism for the reliability of ICs and systems. A thermal protection module for the automotive ICs is reported in this paper. Dual channel detection and decision scheme was designed based on band gap voltage reference. Precision thermal protection point was set by serial resistors and the variations of power supply, temperature and the process were removed by the resistor ratio. The thermal protection module was implemented in CSMC 0.5 [Formula: see text] 60 V BCD process, incorporated in a CAN transceiver chip. The area of the module was about 0.02 mm2 and thus it was very compact and low cost to integrate in chips. The performance of the thermal protection parameters was measured in incubators. The thermal shutdown temperature was about 164.4[Formula: see text]C and the thermal recovery temperature was about 153[Formula: see text]C with hysteresis temperature of 10 K. Additionally, the thermal protection module showed good consistency with different chips.

A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology

The need for a novel multi-scale ESD (ElectroStatic Discharge) network recognition and verification methodology is described in this paper. The proposed solution is used to limit the risk of ESD design errors and to enhance IC reliability, independently of the implemented ESD protection strategy and the type of package assembly technique. This method relies on a topology-aware & graph-based verification paradigm which is generic enough to be usable at every step of the design flow. Its efficiency is illustrated with examples involving custom I/O ring portions in 28nm UTBB FD-SOI High-K metal gate technology.

Improvement of Leakage Trip Operation Time through Electronic Circuits Analysis of the Circuit-Breakers for Human Body Protection Against Electric Shock

This paper analyzed the electronic circuit and investigated the electrical properties to improve the tripping time of domestic ELCB. The operating time of the ELCB showed different values according to the location of voltage waveform and the duration time of leakage current at the instant when the leakage input signal is occurred under rated voltage, and the maximum value of the time measured was up to 26 ms. This was due to the time delay of the IC characteristics used in the electronic circuit which is operated only for the reverse half cycle of the sine wave. The authors developed a prototype circuit breaker with optimized delay element and performed an operation test, through which reduction of the ELCB trip time required for the circuit breaker standard by half was possible. Reduction of operating time of ELCB implies improvement of human body protection against electric shock. It is expected that production of safer ELCB will be possible in the future if more advanced and reliable electronic circuit or IC is developed.