Abstract
The need for a novel multi-scale ESD (ElectroStatic Discharge) network recognition and verification methodology is described in this paper. The proposed solution is used to limit the risk of ESD design errors and to enhance IC reliability, independently of the implemented ESD protection strategy and the type of package assembly technique. This method relies on a topology-aware & graph-based verification paradigm which is generic enough to be usable at every step of the design flow. Its efficiency is illustrated with examples involving custom I/O ring portions in 28nm UTBB FD-SOI High-K metal gate technology.
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