Abstract

Spatially resolved precise prediction of local temperature ${T}(\textit {x,y,z})$ is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling (FEM) do provide excellent results, but the calculation is too time-consuming for a structure that involves eight to ten layers of percolating interconnects, especially for fast turn-around reliability modeling. Here, an analytical model that can quickly/accurately determine $\textit {T(x,y,z)}$ will reduce the design time of self-heated modern IC. In this paper, we 1) develop a physics-based electrothermal compact model for ICs to predict $\textit {T(x,y,z)}$ based on the synthesis of effective medium theory, image charge theory, and Rent’s rule; 2) validate our model against 3-D FEM and experimental data; and 3) predict back-end-of-line (BEOL) reliability (i.e., electromigration at each layer) based on the temperature profile. Since our analytical model predicts changes in $\textit {T(x,y,z)}$ with any given IC’s configuration (e.g., interconnect wire length and number distribution, metal volume fraction in BEOL, heat sinks mechanisms, materials, and type of devices), it suggests new opportunities for optimization of performance and reliability of modern ICs.

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