A new framework of physics-based compact model predicts reliability of self-heated modern ICs: FinFET, NWFET, NSHFET comparison

Abstract

Self-heating effects (SHE) has emerged as an unfortunate corollary of confined-gate transistors (e.g. FinFET; Nanowire-FET, NWFET; NanoSheet-FET, NSHFET) needed for electrostatically-robust sub-10nm ICs [1-3]. The IC-specific SHE reflects increasing thermal resistances (R th ) associated with all three tiers (i.e., transistor, circuit, and system) of the hierarchy. Many groups have developed tier-specific thermal models, which can neither predict the junction temperature (T j ) accurately nor suggest innovative strategies to reduce T j by identifying/removing thermal bottlenecks in the hierarchy. In this paper, we develop computationally efficient, physics-based compact models for each tier, and then stack them to estimate T j — dictated performance/reliability of sub-10nm technologies. Specifically, we (i) refine thermal compact model for front-end-of-line (FEOL) level (TCM F ) based on 3D FEM transient thermal simulations; (ii) investigate SHE by BSIM-CMG circuit simulation for ICs with refined FEOL model; (iii) develop a physics-based thermal compact model for back-end-of line (BEOL) interconnects and interposers (TCM B ) by using image charge and effective medium theory (EMT). The TCM F and TCM B are then integrated to predict T j -specific ICs reliability (i.e., NBTI, HCI, EM) for 14,10, and 7nm FinFETs, NWFETs, and NSHFETs; and finally (iv) we propose various mitigation strategies using thermal shunts to suppress SHE. Our work demonstrates that NSHFET is a good candidate at sub-10nm nodes considering both lower subthreshold swing (SS) than that of FinFET and better reliability than that of NWFET.