Reliability Of Flip Chip Package Research Articles

Influence of Thermally Aged Underfill on Flip-Chip Packages

Underfill material plays a crucial role in flip-chip package reliability, thus it necessary to accurately understand the mechanical properties. The material itself is nonlinear and is dependent on degree of cure, temperature, strain rate and thermal aging, among others. In this work, two underfill materials were characterized for thermal expansion and viscoelastic properties over a wide temperature range. A second set of each material was thermally aged through flip-chip processing steps and 250 thermal cycles and then characterized. Temperature dependent thermal expansion and timetemperature dependent moduli curves were generated to represent each material type. These material models were then implemented into a nonlinear finite element model of a flip-chip package to evaluate package stress interaction through processing steps and thermal cycling. The influence that each underfill material had with and without thermal aging was analyzed with respect to typical package failure mechanisms.

Board Level Reliability of Flipchip Package

In the world of electronic materials, solder is a critical material that plays an important role in the first level (silicon to package substrate) and second level (package to printed circuit board) interconnection. As a joining material in electronic assemblies, solder provides electrical and mechanical connections. The increasing need for reliable electronic devices for harsh environment triggers the need for reliable solder joints. This study focuses on reliability of second level interconnections between package and printed circuit boards. Board level temperature cycling and mechanical drop performance of a 15 mm x 15 mm FCBGA test vehicle were evaluated with different package construction (lidded vs non-lidded), and BGA solder alloys (SA1, SA2, and SA3). Daisy chain packages were assembled on 1.0 mm thick PCB. Mounted units were thermally cycled between from -40C to 125C. Additional samples were evaluated in mechanical drop test conditions following JEDEC standards. Results showed that packages with SA2, and SA3 BGA had significantly higher board-level thermal cycling life compared to SA1. The best drop performance was achieved with SA1 solder. The performance trend among different solder alloys was found to be similar between lidded vs non lidded package. However, lidded package showed improved board-level reliability performance compared to a non-lidded package.

The Effect of Leveler in Cu Electroplating Solution on the Bump Reliability of Flip Chip Packaging

From the previous studies [1,2], it was well known that the voids at the interface of copper (Cu) and tin-silver (Sn-Ag) severely affects the bump reliability of flip chip packaging. And it was also suggested that impurity atoms existing in electroplated Cu film accelerate those voids formation [3]. So, in this study, we investigated the impact of leveler of Cu electroplating solution on the non-metallic impurities of electroplated Cu film and the voids at the interface of Cu and Sn-Ag solder was studied. We have found that the non-metallic impurity concentration was dominantly influenced by the adsorption characteristics of leveler. Fig. 1(a) shows the non-metallic impurity concentration in the electroplated Cu films using the electroplating solution containing different leveler. We can lower the total non-metallic impurity concentration to 14.9 ppm by changing the leveler. And we confirmed that 90% of voids at the interface of Cu and Sn-Ag solder can be reduced even after high temperature storage test at 150°C for 1000 hours, as shown in Fig. 1(b). Reference [1] C.Y. Liu, K.N. Tu, T.T. Sheng, C.H. Tung, D.R. Frear, P. Elenius, J. Appl. Phys. 87, 750 (2000)[2] P.S. Teo, Y.-W. Huang, C.H. Tung, M.R. Marks, T.B. Lim, 50th Electronic Components and Technology Conference, Las Vegas, NV, USA, p. 33 (2000)[3] T. Laurila, V. Vuorinen, J.K.Kivilahti, Mater. Sci. Eng. R, 49, 1 (2005) Figure 1

Reliability Impacts on Flip Chip Packages: Moisture Resistance, Mechanical Integrity and Photo-Sensitive Polyimide (PSPI) Passivation

In this paper, the effects of moisture sensitivity during preconditioning (30 °C/60% RH, 192 hours) tests and material property changes after reliability stressing on flip chip chip-scale package (FCCSP) were comprehensively investigated by various experimental data as well as theoretical explanation. Since the integrity of FCCSP is dependent on the mechanical integrity of underfill and PCB used in package assembly process, deep insight was given on the material properties in order to understand degradation mechanism induced by the combined stresses of preconditioning test and environmental stresses in a sequence. As a result of DOE (Design of Experiment) for 2 different PCB, failures were found only in J PCB because of a large CTE change before and after moisture absorption. After moisture absorption, large CTE change from 27.78 to 32.04 of J PCB could aggravate the thermal mismatch between a PCB and an underfill, it caused shear displacement by more than 2,309 ppm in the interface. According to the DOE for underfill, we verified that higher modulus underfill could improve the reliability of flip chip packages. Based on our works, we recommend the optimized value for underfill modulus is from 8 GPa to 12 GPa. We explained logically two different failure mechanisms of delamination. One is induced by CTE mismatch of PCB, and the other is by underfill modulus by means of electron microscope. Finally, as to reliability concerns of moisture resistance arisen from the absence of the photo-sensitive polyimide (PSPI) passivation layer, we demonstrated that potential risk is minimal if FCCSP is assembled with an appropriate underfill as well as PCB.

Interfacial reaction and failure mechanism of Cu/Ni/SnAg1.8/Cu flip chip Cu pillar bump under thermoelectric stresses

Micro-interconnection copper pillar bumps are being widely used in the packaging areas of memory chip and high performance computer due to their high density, good conductivity and low noise. Studying the interfacial behavior of copper pillar bump is of great significance for understanding its failure mechanism and microstructure evolution in order to improve the reliability of flip chip package. The thermoelectric stress test, in-situ monitor, infrared thermography test, and microstructure analysis method are employed to study the interfacial reaction, life distribution, failure mechanism and their effect factors of Cu/Ni/SnAg1.8/Cu flip chip copper pillar interconnects under 9 groups of thermoelectric stresses including 2104-3104 A/cm2 and 100-150℃. Under thermoelectric stresses, the interfacial reaction of Cu pillar can be divided into three stages:Cu6Sn5 growth and Sn solder exhaustion; the Cu6Sn5 phase transformation, exhaustion and the Cu3Sn phase growth; voids formation and crack propagation. The rate of Cu6Sn5 phase transforming into Cu3Sn phase is positively correlated with the current density. There are four kinds of failure modes including Cu pad consumption, solder complete consumption and transformation into Cu3Sn, Ni plating layer erosion and strip voids. An obvious polar effect is observed during the dissolution of Cu pads on the substrate side and the Ni layer on the Cu pillar side. When Cu pad is located at the cathode, the direction of electron flow is the same as that of the heat flow, and it can accelerate the consumption of Cu pad and the growth of Cu3Sn. When Ni layer serves as the cathode, the electron flow can enhance the consumption of Ni layer. Under 150℃ and 2.5104 A/cm2, the local Ni barrier layer is eroded after 2.5 h, which results in the transformation of Cu pillar on the Ni side into (Cux, Niy)6Sn5 and Cu3Sn alloy. The life of Cu pillar interconnection complies well to the 2-parameter Weibull distribution with a shape parameter of 7.78, which is a typical characteristic of cumulative wear-out failure. The results show that the intermitallic growth behavior and failure mechanism at Cu pillar interconnects are significantly accelerated and changed under thermoelectric stresses compared with the scenario under the single high temperature stress.

Measurement of underfill interfacial and bulk fracture toughness in flip-chip packages

Flip-chip package reliability is greatly improved by encapsulating the solder interconnections between a polymeric encapsulant or underfill. However, thermo-mechanical stresses within such packages often lead to failures initiating in the vicinity of chip and underfill interface. In this study, we present experimental results geared towards measuring and understanding such failure mechanisms. We provide the bulk fracture toughness of the underfill material and interfacial fracture toughness between the underfill material and the silicon die. The bulk and interfacial fracture toughness measurements are performed as a function of temperature. We use the single edge notch bending test to calculate the bulk fracture toughness of the underfill and to measure the interfacial fracture toughness, we use a novel technique referred to as the wedge delamination method. The wedge delamination method provides substantial advantage in measuring the interfacial fracture toughness for brittle materials over traditional methods. Using the wedge delamination method we compare the fracture strength between the underfill and silicon at the front-face and side-wall interfaces. Additionally, the influence of dicing technique on fracture toughness is also investigated.

Effect of ILU dispensing types for different solder bump arrangements on CUF encapsulation process

Underfill encapsulation play an important role to improve the reliability of flip chip package, yet the conventional underfill (CUF) encapsulation process is subjected to several drawbacks such as extended filling time, incomplete filling and voids formation. Therefore, the focal point of this project is on the study of different CUF dispensing method for different types of ball grid array (BGA) orientations. The experimental works and numerical simulations were performed to predict the interaction of fluid on the structure and the results from both studies have reached a good agreement. This paper explores the effect of BGA orientations and dispensing types namely I, L and U on the behavior of underfill flow and the filling time. This study reveals the potential of both aspects in improving the efficiency of CUF encapsulation. The findings show that of all 9 different combinations of orientations and dispensing type, the fastest filling time is achieved by combining perimeter orientations with U-type flow. However, it suffers from racing effect that might lead to possible voids formation. The findings are then applied on real size 16×16 BGA and it was found that the flow front propagation changed from concave to convex shape for small size BGA and the filling time is also highly dependent on the BGA size and the solder ball count.

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

Study on Bump Arrangement to Accelerate the Underfill Flow in Flip-Chip Packaging

Flip-chip packaging is an integrated circuit packaging technique that uses solder bumps to connect chip with substrate. The underfill process uses epoxy encapsulant to solve this problem and improves the reliability of flip-chip packaging. The encapsulant is filled into the gap between the chip and substrate by the capillary force so that the thermal stresses may disperse into the underfill materials to avoid crack generation. The filling time in the underfill process strongly depends on the arrangement of the solder bumps. The edge effect can enhance the filling speed during the underfill encapsulation if the void formation can be avoided. With distributed bump pitch design, the filling time of the underfill can be reduced. There exists an optimal selection of the pitch variation during the use of distributed bump pitch. Another method of using a center bump-free channel can also increase the filling efficiency. The optimization method is used to determine the size of the channel that is found to increase the filling speed dramatically in the case of underfill of the chip with a fine bump pitch.

Mid-end Process Technologies for Advanced Packaging of LSI Devices

As the demand for advanced packaging is growing, the value of mid-end process technologies is increasing in an effort to realize innovative device products. Substrate-free packaging and 3D integration are coming with the challenges to polymer resin deposition for interlayer dielectrics films and final passivation films and their developments of process integration. For cost reduction of Fan-out Wafer Level Packaging, we have demonstrated thick film deposition on square panel substrates using the photo-sensitive resin materials tailored to spray-coating and slit-coating. Chip stacking of a high performance logic chip on a high band-width DRAM needs fine pitch patterning of a thick photo-resist for Cu electroplated redistribution lines on the DRAM. Our successful process integration has confirmed that slight oxidation of the Cu seed surface to form Cu2O is preferred to improve adhesion between the resist and the Cu surface. Finally, the restoration of plasma damaged surface of a polymer final passivation film on advanced low-k chips to improve reliability of flip chip packages has been discussed as one of typical examples of materials design for process integration.

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 mum), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.

Optimization of Thermomechanical Reliability of Board-Level Flip-Chip Packages Implemented With Organic or Silicon Substrates

A design that optimizes package-level along with board-level thermomechanical reliability of a flip-chip package implemented with an organic or a silicon substrate is provided for the package subjected to an accelerated thermal cycling test condition. Different control factors including thickness of substrate, die, board, and polyimide or soldermask are considered. The optimal design is obtained using an L9 (34) orthogonal array according to the Taguchi optimization method. Importance of each of these control factors is also ranked.

Calibration of Electromigration Reliability of Flip-Chip Packages by Electrothermal Coupling Analysis

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black’s equation to calibrate the experimental electromigration fatigue lives.

Thermal and hygroscopic reliability of flip-chip packages with an anisotropic conductive film

Thermal and hygroscopic reliability of anisotropic conductive film (ACF) joints in relation to flip-chip bonding force was evaluated by thermal shock and constant temperature/humidity testing. The failure mode by thermal shock testing varied with increasing bonding force, i.e., (1) formation of a conduction gap between conductive particles and Au bump or Ni/Au plated Cu pad at low bonding force and (2) delamination of adhesive matrix from the plated Cu pad on the flexible substrate at high bonding force. The delamination initiated as a crack under a conductive particle and propagated sideward resulting in a complete delamination of the ACF from the Cu pad. However, delamination was observed between the ACF and Au bump on the chip side after the constant temperature/humidity testing for 500 h. A theoretical calculation was also conducted to predict the connection resistance of the ACF joint before and after reliability tests. The calculation showed the importance of the bonding gap between the electrodes.

Effect of bonding force on the reliability of the flip chip packages employing anisotropic conductive film with reflow process

Thermo-mechanical reliability of flip chip packages employing anisotropic conductive film (ACF) was investigated in terms of the effect of bonding forces on the failure mode of the packages. Conventional reflow process was conducted to evaluate the reliability of the package. Two kinds of failure modes were detected in this study. The first one is formation of a conduction gap between conductive particle and Ni/Au plated Cu pad, while the second one is delamination of the adhesive matrix from the plated Cu pad on flexible substrate. The determination of the failure mode was mainly affected by the variation of the bonding force. In case of the ACF joints with lower bonding forces, a conduction gap was the main failure mode of the reflowed joints, while the delamination of the adhesive matrix was frequently observed in case of the joints with higher bonding forces. The difference in failure mode was discussed in the main text.

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.

Reliability of Flip Chip Package with Underfills under Thermal Shock

The thermal fatigue properties of the solder joints with various underfills were evaluated by thermal shock test. Flip chip package with electroless nickel-immersion gold plated on Cu pad of FR-4 substrate and the Sn-37Pb solder ball was used. The thermal fatigue crack initiated at the edges of interface between solder and silicon die. The fatigue property of package with underfill, which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) value was better than that of package with underfill having a lower Tg and higher CTE.

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration

This paper investigates the electromigration reliability of flip chip packages with and without pre-bump wafer probing via high temperature operation life test (HTOL) using printed and electroplated bumps. Under bump metallization (UBM) of printed and electroplated bumps is a thin film of Al/Ni(V)/Cu and Ti/Cu/Ni, respectively, while the bump material consists of eutectic Sn/Pb solder. Current densities from 7380 to 20 100 A/cm 2 and ambient temperatures at 100, 125 and 150 °C are applied in order to study their impact on electromigration. The results reveal that the bump temperature has a higher influence than the current density when it comes to bump failures. The observed interconnect damage is from bumps with electrical current flowing upward into the UBM/bump interface (cathode). Identified failure sites and modes reveal structural damage at the region of the UBM and UBM/bump interface, in the form of solder voiding and cracking. The effects of current polarity, current crowding, and operation temperature are key factors to electromigration failures of flip chip packaging. The maximum allowable current density of the electroplated bumps is superior to the printed bumps by a factor of 3.0–3.7 times. Besides, the median time to failure (MTTF) of without-underfill packaging is preferred to that of with-underfill packaging by 1.5–2.2 times. Furthermore, the differences in MTTF between pre-bump and without pre-bump probing procedures are 2.0–19.4% and 1.6–10.3% for printed and electroplated bumps, respectively.

Selection of Proper Fatigue Model for Flip Chip Package Reliability

There have been diverse fatigue models and approaches to properly estimate solder joint reliability. However, it is one of the most difficult problems to determine which solder constitutive models and fatigue models can be applied best. In this paper, both viscoplastic and elastic-plastic-creep solder constitutive models could be utilized to calculate accumulated inelastic response under 208 K to 423 K(-65 °C to 150 °C) thermal cycling condition. And two different fatigue models, Darveaux and creep-fatigue model were applied to find solder joints fatigue life for flip chip assembly. Moreover, each fatigue life was compared to experimental result for the validation of finite element analysis. The actual number of cycles to failure was obtained from cross sectional view of the package with SEM.