Reliability Of Electronic Devices Research Articles

Enhancement of Cu-to-Cu bonding property by residual stress in Cu substrate

This study investigated the use of copper nanoparticles (Cu NPs) as a novel material for interconnecting joints in advanced electronic packaging technology. Cu NPs offered a promising alternative due to their excellent electrical and thermal properties. Cu NPs were characterized as single crystals by a transmission electron microscope, and electron backscatter diffraction confirmed that the grain size of the Cu substrate was about 11 μm and only became slightly larger after thermal annealing. Surface diffusion was determined to be the dominant kinetic path for Cu NP sintering on the substrate. An additional driving force for sintering was validated by measuring the stress state using X-ray diffraction. The characterization results provided evidence for proposing a mechanism to explain how residual stress influenced atomic behavior during the sintering process. High residual stress enhanced the strength of the Cu NP joints and improved the reliability of electronic devices.

AutoDetect: Novel Autoencoding Architecture for Counterfeit IC Detection

AbstractThe global electronic supply chain industry is a complex and interconnected network of companies, organizations, and individuals that collaborate to produce and distribute electronic devices and components. It plays a critical role in the global economy, as electronic devices have become an essential part of modern life. Electronic components and devices are produced and distributed across the world, with different regions and countries specializing in different aspects of the supply chain. This global nature of the electronic supply chain industry also poses challenges, particularly in terms of quality control and supply chain transparency involving counterfeit components owing to its interconnected nature. Counterfeiting of integrated circuits (ICs) and semiconductor devices is a significant challenge that poses threats to the safety and reliability of electronic devices, the global economy, intellectual property rights, and the overall sustainability of the electronic supply chain industry. To address this challenge, we propose a novel autoencoding architecture for counterfeit IC detection using a labeled database. The proposed architecture achieves an overall accuracy of 83% which is $$\approx$$ ≈ 20% more than the existing transfer learning approaches.

Influence of Sn grain orientation on mean-time-to-failure equation for microbumps in 3D IC technology

The mean-time-to-failure (MTTF) associated with microbumps is a pivotal factor influencing the reliability of cutting-edge consumer electronic devices. Within Sn-based solder joints, the orientation of Sn grains significantly impacts the diffusion velocity of Cu and Ni atoms, thereby impacting MTTF. While a large solder joint encompassing numerous Sn grains can be treated as isotropic, the scenario shifts in a small microbump with just one Sn grain, rendering it anisotropic. In such cases, the Sn grain orientation emerges as a dominant factor dictating the microbump's longevity. Herein, we investigated the influence of Sn grain orientation on MTTF of electromigration, thermomigration, and thermal aging. A new parameter, α, was introduced, which signifies the angle between the c-axis of the Sn grain and the direction of external stressing.

Toward Ideal Low-Frequency Noise in Monolayer CVD MoS2 FETs: Influence of van der Waals Junctions and Sulfur Vacancy Management.

The pursuit of sub-1-nm field-effect transistor (FET) channels within 3D semiconducting crystals faces challenges due to diminished gate electrostatics and increased charge carrier scattering. 2D semiconductors, exemplified by transition metal dichalcogenides, provide a promising alternative. However, the non-idealities, such as excess low-frequency noise (LFN) in 2D FETs, present substantial hurdles to their realization and commercialization. In this study, ideal LFN characteristics in monolayer MoS2 FETs are attained by engineering the metal-2D semiconductor contact and the subgap density of states (DOS). By probing non-ideal contact resistance effects using CuS and Au electrodes, it is uncovered that excess contact noise in the high drain current (ID) region can be substantially reduced by forming a van der Waals junction with CuS electrodes. Furthermore, thermal annealing effectively mitigates sulfur vacancy-induced subgap density of states (DOS), diminishing excess noise in the low ID region. Through meticulous optimization of metal-2D semiconductor contacts and subgap DOS, alignment of 1/f noise with the pure carrier number fluctuation model is achieved, ultimately achieving the sought-after ideal LFN behavior in monolayer MoS2 FETs. This study underscores the necessity of refining excess noise, heralding improved performance and reliability of 2D electronic devices.

Effect of Creep, Fatigue and Random Vibration on the Integrity of Solder Joints in BGA Package

This study employs Finite Element Analysis (FEA) to investigate the effects of creep, fatigue, and random vibration on the integrity of solder joints in BGA packages in electronic modules. Evaluating the response of lead-based Sn63Pb37 and lead-free SnAgCu alloy solders (SAC305, SAC387, SAC396, and SAC405) to induced loads - stress, strain, strain energy density, and displacement in the joints is obtained and studied better to understand the mechanism of the joints' degradation. SAC305 and SAC405 are modelled with linear stress-temperature relationships σ = 3.152T–68.167 and σ = 1.543T–34.983, respectively. The magnitude of the strain energy density in the joints is a key failure driver. SAC387 and SAC396 solder joints display lower values of strain energy density and thus have higher durability. Displacement analysis indicates that SAC305 and Sn63Pb37 are prone to deformation-induced failure. SAC387 exhibits the highest fatigue yield stress at 58 MPa, while SAC405 displays the lowest stress at 22 MPa. Analysis of the results of random vibration shows that Sn63Pb37 developed the highest stress at 34.62 MPa and is thus susceptible to stress-induced failure. The robust stress, strain, and strain energy responses of SAC405 and SAC396 provide key insights into improving the mechanical reliability of future electronic devices towards better sustainability.

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Effects of Cu/SnAgCu Powder Fraction and Sintering Time on Microstructure and Mechanical Properties of Transient Liquid Phase Sintered Joints.

The effects of the sintering duration and powder fraction (Ag-coated Cu/SnAgCu) on the microstructure and reliability of transient liquid phase sintered (TLPS) joints are investigated. The results show that two main intermetallic compounds (IMCs, Cu6Sn5 and Cu3Sn) formed in the joints. The Cu6Sn5 ratio generally decreased with increasing sintering time, Cu powder fraction, and thermal treatment. The void ratio of the high-Cu-fraction joints decreased and increased with increasing sintering and thermal stressing durations, respectively, whereas the low-Cu-fraction counterparts were stable. We also found that the shear strength increased with increasing thermal treatment time, which resulted from the transformation of Cu6Sn5 and Cu3Sn. Such findings could provide valuable information for optimizing the TLPS process and assuring the high reliability of electronic devices.

Neural Network-Based Approach for Failure and Life Prediction of Electronic Components under Accelerated Life Stress

Researchers worldwide have been focusing on accurately predicting the remaining useful life of electronic devices to ensure reliability in various industries. This has been made possible by advancements in artificial intelligence (AI), machine learning, and Internet of Things (IoT) technologies. However, accurately forecasting device life with minimal data sets, especially in industrial applications, remains a challenge. This paper aims to address this challenge by utilizing machine learning algorithms, specifically BP, XGBOOST, and KNN, to predict device reliability with limited data. The remaining life dataset of electronic components is obtained through simulation for training and testing the algorithms, and the experimental results show that the algorithms achieve a certain level of accuracy, with the error rates being as follows: BP algorithm, 0.01–0.02%; XGBOOST algorithm, 0.01–0.02%; and KNN algorithm, 0–0.07%. By benchmarking these algorithms, the study demonstrates the feasibility of deploying machine learning models for device life prediction with acceptable accuracy loss, and highlights the potential of AI algorithms in predicting the reliability of electronic devices.

BN green gel thermal interface material with high thermal conductivity and low thermal contact resistance for efficiently thermal management

As an important component of electronic devices, thermal interface materials (TIMs) provide a fast heat dissipation channel, which will significantly improve the reliability and long-term stability of electronic devices. Gel TIMs with good flexibility is a development direction for thermal management in the future. However, the green and environmental issues in the preparation of gel TIMs with good stability are also important problems that must be considered. Here, combining the advantages of green deep eutectics solvents and high thermal conductivity boron nitride, a boron nitride polymerizable deep eutectics solvents gel composite TIMs with high thermal conductivity, good stability and low thermal contact resistance (TCR) has been developed. The thermal conductivity of composite TIMs achieved 1.18 W/m·K at a boron nitride loading of 20 wt%. Under pressure gradient testing (10 Psi-50 Psi), the TCR of composite TIMs decreased to 0.76 K·cm2/W. In the temperature gradient test (30 °C-70 °C), the TCR of the composite TIMs dropped to 0.143 K·cm2/W. Furthermore, in the TCR cycling test, the composites showed better cycling stability. In addition, composite TIMs also show better thermal performance in practical applications. This work provides a green way for the fabrication of gel TIMs with high thermal conductivity, good stability and low TCR.

Effect of temperature modulation on the performance of top contact bottom gate organic thin film transistor

This research article investigates the influence of temperature variations on the performance parameters of Top Contact Bottom Gate (TCBG) Organic Thin Film Transistors (OTFTs). Employing the Arrhenius equation and Schottky emission model, the study explores temperature-dependent charge carrier mobility and injection mechanisms. Analyzing a wide range of parameters, the research unveils a complex interplay between temperature and OTFT behavior. The linear and saturation mobilities exhibit a decline due to enhanced carrier-phonon interactions and lattice vibrations. Transconductance and ION/IOFF ratio display a concomitant decrease at higher temperatures, indicative of the heightened susceptibility of OTFT performance to temperature fluctuations. The depreciation in subthreshold slope and threshold voltage with rising temperatures underscores the influence of temperature on trap states. The research emphasizes the importance of considering temperature’s impact during OTFT design for diverse applications, enhancing the reliability and functionality of organic electronic devices.

Thermal enhancement of microchannel heat sink using pin-fin configurations and geometric optimization

The microchannel heat sink (MCHS) is a robust cooling technique that ensures the efficiency and reliability of compact electronic devices by dissipating a large amount of heat because of its high surface area-to-volume ratio. This study proposes a novel modification of the pin-fins geometry in MCHS, and geometric optimization using response surface methodology (RSM) to build a low thermal resistant MCHS with enhanced heat transfer efficiency with low-pressure drop. Three dimensional numerical simulations using ANSYS FLUENT 2021 R2 are performed on three pin-fins configurations, i.e., MC-BW (pins mounted transversely to the bottom wall), MC-SW (pins mounted transversely to the side wall), and MC-Mixed (pins mounted transversely to the bottom and side wall). The thermal and flow characteristics are investigated using a laminar conjugate heat transfer model at Reynolds numbers 100–1000. Results show that introducing pin-fins significantly enhances heat dissipation as it continuously breaks the boundary layer and generates flow separation downstream of the pin-fins, which enhances fluid mixing and increases heat transfer augmentation inside MCHS. Among different configurations, the MC-Mixed gives the highest improvement of 50% in the convective heat transfer coefficient at Re = 1000. The highest thermal enhancement factor of η = 1.4 is obtained for the MC-Mixed configuration at Re = 600. For the base wall pin fin configuration RSM yields optimized values of 2.50 mm, 0.25 mm, and 0.045 mm for transverse pitch, longitudinal pitch, and diameter of pin respectively, and for the mixed pin fin configuration it gives 1.0 mm, 0.150 mm, 0.035 mm and 1.250 mm values for transverse pitch, longitudinal pitch, diameter of pin and pitch of side wall pins respectively for the maximum heat transfer and minimum pressure drop.

A Comparative Numerical Analysis of Cold Plates for Thermal Management of Chips With Hotspots

Abstract Thermal and hydraulic performances of seven water-cooled minichannel cold plates with different internal structures are compared using numerical analysis. Recent increasing demands for high-performance computing have led to serious challenges in the thermal management of electronic devices. In addition to dangerous on-chip temperatures, heterogeneous integration and local regions of elevated temperatures (hotspots) lead to nonuniform chip-level temperature distributions. As a result, the lifespan and reliability of electronic devices are adversely impacted. Due to the limitation of the air-cooled heat sinks, several new methods, such as liquid-cooled microchannel cold plates are developed to remedy these challenges. The objective of this work is to provide a comparative numerical study of the effectiveness of different minichannel cold plate internal structures in the thermal management of a chip with a nonuniform power map and a hotspot. Cold plate thermal resistance, on-chip temperature uniformity, and pump power were the metrics used for this comparison. For four coolant inlet flow rates within the laminar regime, it is seen that increasing the inlet flowrate enhances the thermal resistance of all cold plate designs while creating less uniformity in chip-level temperature distribution relative to the conventional straight microchannels. Concentrating pin fins on the hotspot showed a 7.2% reduction in thermal resistance, despite increasing temperature nonuniformity by about 7.6%. However, it is observed that hotspot-focused pin fins are more effective in lowering the chip's maximum temperature. Obtaining lower chip-level nonuniformity may be possible by modifying the inlet and outlet conditions of the cold plates.

Vulnerability Detection in Cyber-Physical System Using Machine Learning

The cyber-physical system is a specific type of IoT communication environment that deals with communication through innovative healthcare (medical) devices. The traditional medical system has been partially replaced by this application, improving healthcare through efficiency, accessibility, and personalization. The intelligent healthcare industry utilizes wireless medical sensors to gather patient health information and send it to a distant server for diagnosis or treatment. The healthcare industry must increase electronic device accuracy, reliability, and productivity. Artificial intelligence (AI) has been applied in various industries, but cybersecurity for cyber-physical systems (CPS) is still a recent topic. This work presents a method for intelligent threat recognition based on machine learning (ML) that enables run-time risk assessment for better situational awareness in CPS security monitoring. Several machine learning techniques, including Nave Bayes (65.4\%), Support Vector Machine (64.1%), Decision Tree (89.6%), Random Forest (92.5%), and Ensemble crossover (EC) XG boost classifier (99.64), were used to classify the malicious activities on real-world testbeds. The outcomes demonstrate that the Ensemble crossover XG boost enabled the best classification accuracy. When used in industrial reference applications, the model creates a safe environment where the patient is only made aware of risks when categorization optimism exceeds a specific limit, minimizing security managers' pressure and efficiently assisting their choices.

Investigating the preferential growth of Bi grains in Sn-Bi based solder under thermal aging

SnBi based solders have attracted widespread attention due to their promising applications in heterogeneous integration and three-dimensional microelectronic packaging. However, the low melting point of SnBi based solder means their high homologous temperature during service, leading to fast coarsening of the microstructure, which can significantly impair the reliability of electron devices. It has been found that Bi grains in SnBi based solder interconnects grow significantly and exhibit a preferred orientation under thermal loading conditions, but the mechanisms underneath the preferential growth of Bi grains is yet to be understood. In this work, a phase field model incorporating the thermal stress effect is developed and employed to investigate the dynamic evolution of the microstructure of SnBi solder under thermal aging, and to capture the morphology changes of the grains with different orientations. It is demonstrated that Bi grains with c-axis parallel to the z-axis preferentially exist in eutectic SnBi solder under thermal aging, and Bi grains with a large angle between the c-axis and the z-axis are swallowed by the preferred grains. Moreover, there is a competitive evolution between grains with different orientations in the polycrystalline eutectic SnBi solder, due to the minimization of system elastic strain energy. Further mechanism analysis elucidates that the Bi grain orientation preference in SnBi solders is caused by the dependence of their Young’s modulus and coefficient of thermal expansion on the grain orientation, the favored grains possess a lower strain energy compared to other grains.

Temperature and current density prediction in solder joints using artificial neural network method

Purpose Due to the miniaturization of electronic devices, the increased current density through solder joints leads to the occurrence of electromigration failure, thereby reducing the reliability of electronic devices. The purpose of this study is to propose a finite element-artificial neural network method for the prediction of temperature and current density of solder joints, and thus provide reference information for the reliability evaluation of solder joints. Design/methodology/approach The temperature distribution and current density distribution of the interconnect structure of electronic devices were investigated through finite element simulations. During the experimental process, the actual temperature of the solder joints was measured and was used to optimize the finite element model. A large amount of simulation data was obtained to analyze the neural network by varying the height of solder joints, the diameter of solder pads and the magnitude of current loads. The constructed neural network was trained, tested and optimized using this data. Findings Based on the finite element simulation results, the current is more concentrated in the corners of the solder joints, generating a significant amount of Joule heating, which leads to localized temperature rise. The constructed neural network is trained, tested and optimized using the simulation results. The ANN 1, used for predicting solder joint temperature, achieves a prediction accuracy of 96.9%, while the ANN 2, used for predicting solder joint current density, achieves a prediction accuracy of 93.4%. Originality/value The proposed method can effectively improve the estimation efficiency of temperature and current density in the packaging structure. This method prevails in the field of packaging, and other factors that affect the thermal, mechanical and electrical properties of the packaging structure can be introduced into the model.

A Novel Thermal Management Method for Enhancing the Consistency of IGBT Heat Stress in Converter

The reliability of power electronic devices and converters is closely related to thermal stress. However, the research on IGBT heat balance in the converter is still insufficient. To address this problem, a novel thermal management method for enhancing the consistency of IGBT heat stress in a converter is proposed in this paper. A converter-level method based on the bus voltage ringing is utilized for the IGBT junction temperature monitoring. The IGBT power loss can be controlled by modulating the switching frequency, thus IGBT temperature can be adjusted to improve the IGBT thermal consistency of the converter. The validity of the proposed method is verified by experiments with unbalanced load and unbalanced thermal impedance for a three-phase inverter. Besides, the transient process and steady-state performance with asynchronous switching frequency are demonstrated. The method proposed can enhance the thermal consistency effectively and be promising for improving the reliability of the converter with little effect on the performance.

Radio frequency-assisted curing of on-chip printed CNT/silicone heatsinks produced by material extrusion 3D printing

With the rapid development of high-power integrated electronic devices, many polymer-based thermal management devices have been developed to address the problem of overheating and to improve the reliability and lifetime of electronic devices. Here we demonstrate the material extrusion 3D printing of carbon nanotube (CNT)/silicone heatsinks directly onto electronic devices. CNTs were used as a conductive nanofiller and a rheological modifier to improve thermal and electrical conductivities and the printability of the silicone inks, respectively. Additionally, CNTs are also a radio frequency (RF) susceptor, so the integration of CNTs into the silicone matrix allowed for rapid out-of-oven curing by applying RF heating. Specifically, at a CNT loading of 14 wt%, the CNT/silicone heatsinks could be printed and RF cured with shape retention; the heatsinks’ performance was comparable to that of commercial heatsinks. More importantly, the CNT/silicone heatsinks could be printed and cured directly onto a chip attached to a circuit board. This printing approach can eliminate the use of thermal interface materials and the step of heatsink assembly while reducing the number of thermal interfaces between the chip and the heatsink. The results suggest that material extrusion 3D printing combined with RF-assisted curing can be an effective approach to fabricate high-performance polymer-based heatsinks with reduced production time and energy requirements.

Transient thermal behavior of a passive heat sink integrated with phase change material: A numerical simulation

This paper presents a numerical investigation of the thermal performance of a heat sink augmented with phase change material (PCM) for passive electronic cooling applications. The PCM-based heat sink employed N-eicosane as the PCM, which has a suitable melting temperature and high latent heat capacity for electronic cooling applications. A numerical simulation based on the enthalpy-porosity method was developed to analyze the impact of both PCM inclusion and induced natural convection airflow on the base temperature of the heat sink. The operational conditions were selected as three constant heat fluxes of 2, 3, and, 4 kW/m2 and four critical base temperatures of 40, 45, 50, and 55 °C. The influence of fin numbers on the thermal behavior of both PCM-based and conventional (without PCM) heat sinks was also investigated by considering the three fin numbers of 4, 5 and, 6. The PCM integration into the heat sink effectively delayed the rise of base temperature and extended the safe operation time compared to a conventional one. The thermal performance enhancement ratio of the PCM-based heat sink over the conventional heat sink ranged from 1.53 to 2.81, depending on the selected heat flux and critical temperature. The effect of fin numbers on thermal performance was more significant at lower heat fluxes. It was observed that the PCM-based heat sinks achieved a higher time-averaged heat transfer coefficient than the conventional heat sinks, and this coefficient increased with the heat flux and decreased with the fin number. For both PCM-based and conventional heat sinks, it was observed that increasing the fin number reduces the heat transfer coefficient value due to the suppressing effect of fins on natural convection current. The results demonstrate the potential of using passive PCM-based heat sinks for improving the reliability and efficiency of electronic devices compared to conventional heat sinks.

Bonding wire characterization using non-destructive X-ray imaging

Counterfeiting in the semiconductor industry poses a significant threat to the economy and can lead to lower performance and reliability of electronic devices. X-ray technology in this respect is commonly used for non-destructive testing to identify physical defects and anomalies in integrated circuits. However, for accurate material identification, destructive methods such as spectroscopic techniques including X-ray diffraction and X-ray fluorescence are typically required. In this work, a fast and non-destructive method is presented for material characterization of bonding wires in ICs and other SMD components by measuring X-ray absorption profiles. The results demonstrated that the X-ray imaging technique can effectively distinguish between bonding wires made of gold, silver, copper, and aluminum. Moreover, the thickness of these materials can also be detected. This technique exhibits high potential for utilization as a simple and quick method for non-destructive material characterization in the industrial environment.

An Analysis of the Significance of the 14N(n, p) 14C Reaction for Single-Event Upsets Induced by Thermal Neutrons in SRAMs

The thermal neutron threat to the reliability of electronic devices caused by <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> B capture is a recognized issue that prompted changes in the manufacturing process of electronic devices with the aim of limiting as much as possible the presence of this isotope nearby device sensitive volumes. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N can also capture thermal neutrons and release low-energy protons (through the <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N(n,p) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> C reaction) that have high enough linear energy transfer to cause single-event upsets (SEU). Typically, nitrogen is used in thin barrier layers made of TaN or TiN or even as insulator in the form of Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> . Numerical simulations on sensitive volumes calibrated on proton and ion experimental data and with an accurate description of the metallization layer on top of the sensitive region show that the presence of nitrogen in these thin barrier layers can be enough to justify the experimentally observed thermal neutron SEU cross section for a static random access memory sensitive to low-energy protons. Nevertheless, the expected SEU cross section from thermal neutrons is usually a few orders of magnitude lower than that of high-energy particles, therefore, not representing an important threat in atmospheric applications. At the same time, for high-energy accelerators, the contribution to the total soft error rate could become substantial, though easy to handle by margins.