Circuit Reliability Research Articles

Regulation system by voltage booster transformer

In this article, the features of the oscillatory circuit are investigated in order to determine the possibility of their application for controlling thrusters when building new, simple and reliable circuits for regulating booster voltage stabilizers from the value of the supply voltage. In Ferro resonant circuits connected to a voltage source with low internal resistance, with a certain combination of parameters, oscillations are excited at the fundamental frequency, the initial phase of which has a shift relative to the initial phase of the applied voltage.

Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction

With the rapid development of semiconductor technology, chip integration is getting beyond imagination. Aging has become one of the main threats to circuit reliability. In order to develop aging degradation prediction, it is critical to evaluate aging to avoid circuit failures. At present, the research on aging prediction is mainly focused at the transistor and gate levels: at transistor level, the precision is high, but the speed is low; whereas, the gate-level accuracy is not high, but the speed is very fast. In this paper, a path-level aging prediction framework based on the novel critical gate is proposed. The 10-year Negative Bias Temperature Instability (NBTI) aging delay of the critical subcircuit extracted by the novel critical gate is obtained, and the aging delay trend is learnt by using a linear regression model. Then the critical path aging delay can be obtained quickly based on the framework developed by machine learning using the linear regression model. The experimental results of ISCAS’85 and ISCAS’89 benchmark circuits based on 45-nm PTM show that the proposed framework is superior to the existing methods.

Compact artificial neuron based on anti-ferroelectric transistor

Neuromorphic machines are intriguing for building energy-efficient intelligent systems, where spiking neurons are pivotal components. Recently, memristive neurons with promising bio-plausibility have been developed, but with limited reliability, bulky capacitors or additional reset circuits. Here, we propose an anti-ferroelectric field-effect transistor neuron based on the inherent polarization and depolarization of Hf0.2Zr0.8O2 anti-ferroelectric film to meet these challenges. The intrinsic accumulated polarization/spontaneous depolarization of Hf0.2Zr0.8O2 films implements the integration/leaky behavior of neurons, avoiding external capacitors and reset circuits. Moreover, the anti-ferroelectric neuron exhibits low energy consumption (37 fJ/spike), high endurance (>1012), high uniformity and high stability. We further construct a two-layer fully ferroelectric spiking neural networks that combines anti-ferroelectric neurons and ferroelectric synapses, achieving 96.8% recognition accuracy on the Modified National Institute of Standards and Technology dataset. This work opens the way to emulate neurons with anti-ferroelectric materials and provides a promising approach to building high-efficient neuromorphic hardware.

Large-Signal Equivalent Circuit for Datacom VCSELs – Including Intensity Noise

Optical interconnects (OIs) continue to require more and more sophisticated driver and receiver electronics as higher baud rates are pushed in datacom, mainly due to the bandwidth stagnation of the optoelectronic components such as the vertical-cavity surface-emitting laser (VCSEL) in the transmitter as well as the photodetector (PD) in the receiver. Another important focus is maintaining high energy efficiency for the OIs. For both cases, a reliable equivalent circuit model for high-speed VCSELs is required for link optimization. This work is an extension of our previously presented large-signal VCSEL equivalent circuit model, where noise is added to the physical processes that the VCSEL model is based on. Thus, a new step is taken in the strive of developing an even more accurate physics-based large-signal VCSEL equivalent circuit model for datacom applications. Following a detailed description of the VCSEL noise modelling, a presentation is given on simulated results of VCSEL relative intensity noise (RIN) spectrum and eye diagrams under 28 Gbaud on-off keying (OOK) and pulse-amplitude 4 (PAM4) modulation, and that are compared with corresponding measurement results. Good agreement is found over a wide range of VCSEL driving conditions and temperatures. A 28-GHz-bandwidth VCSEL is applied for the demonstration, and the presented noise extended VCSEL equivalent circuit model was implemented in Verilog-A, and the simulations were performed using Cadence Spectre.

Analysis of Control Strategy of Three-phase Bridge Fully Controlled Rectifier Circuit Based on PID Control

At the present stage of industrial production in China, rectifier circuits still have an important position, and their safe, reliable, and efficient operation is still a necessary issue to be explored in the development of power electronics technology. Therefore, this paper will build an improved three-phase bridge rectifier circuit based on the traditional three-phase bridge fully controlled rectifier circuit, replacing the thyristor with an insulated gate bipolar transistor (IGBT) under the same basic principle, so that it can be more easily controlled by industrial intelligence. The PID controller is introduced to make the output voltage of the rectifier circuit gradually converge to a certain value by continuously correcting the calculation of the trigger angle α and the calculation of the voltage and current values. The simulation results show that the PI-controlled three-phase bridge fully controlled rectifier circuit model established in the paper makes the output of the circuit eventually stabilize under the influence of the closed-loop control, and the simulation results reach the expected value and show strong robust stability. For industrial applications, improving the safety, reliability, efficiency, and flexibility of bridge rectifier circuits is of good reference in practical engineering applications.

Double-integral sliding mode control of the switched-inductor quasi-Z source boost converter

Compared with the traditional converter, the switching inductance quasi-Z source DC-DC boost converter has the characteristics of wide output voltage, small capacitor size and more reliable circuit. However, in the process of DC voltage boost, the system is prone to high startup impulse voltage, output voltage fluctuation, and other problems. Therefore, a double integral sliding mode control (DISMC) method is proposed. The control method takes the capacitance voltage error, the inductance current error and their sum of single integral and double integral as state variables, and derives the equivalent control law from the sliding mode surface. A Lyapunov function is constructed to analyze the existence conditions of DISMC method. And the effects of abrupt changes of input voltage, negative reference voltage and load power on transient oscillation, steady state error and overshoot of the system are analyzed. This control method solves the non-minimum phase problem of capacitor voltage, so as to improve the start-up performance of the controller and speed up the response of the system. Finally, the superiority and effectiveness of the control method are verified by simulation.

Reliable Online Internal Short Circuit Diagnosis on Lithium-Ion Battery Packs via Voltage Anomaly Detection Based on the Mean-Difference Model and the Adaptive Prediction Algorithm

The safety issue of lithium-ion batteries is a great challenge for the applications of EVs. The internal short circuit (ISC) of lithium-ion batteries is regarded as one of the main reasons for the lithium-ion batteries failure. However, the online ISC diagnosis algorithm for real vehicle data remains highly imperfect at present. Based on the onboard data from the cloud battery management system (BMS), this work proposes an ISC diagnosis algorithm for battery packs with high accuracy and high robustness via voltage anomaly detection. The mean-difference model (MDM) is applied to characterize large battery packs. A diagram of the adaptive integrated prediction algorithm combining MDM and a bi-directional long short-term memory (Bi-LSTM) neural network is firstly proposed to approach the voltage prediction of each cell. The diagnosis of an ISC is realized based on the residual analysis between the predicted and the actual state. The experimental data in DST conditions evaluate the proposed algorithm by comparing it with the solo equivalent circuit-based prediction algorithm and the Bi-LSTM based prediction algorithm. Finally, through the practical vehicle data from the cloud BMS, the diagnosis and pre-warn ability of the proposed algorithm for an ISC and thermal runaway (TR) in batteries are verified. The ISC diagnosis algorithm that is proposed in this paper can effectively identify the gradual ISC process in advance of it.

A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design

The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations.

Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive Attributes

The identification of reliability-critical primary input leads (RCPIs) plays an important role in the testing and prediction of reliability boundaries of logic circuits. This article presents a gate-sensitive-attributes-based approach to estimate the criticality of the primary input leads in combinational circuits to their reliability. Oriented to the input vector, a subcircuit-based traversal method marks the critical input leads of each gate in a circuit. Gate-sensitive attributes and a reverse recursive algorithm quantify the effect of each RCPI on circuit reliability under the input vector. A parallel calculation method based on subcircuits with only one primary output reduces the computational complexity to accelerate the calculation process. Similarity-based clustering avoids unnecessary calculations, and a self-adaptive strategy is used to check convergence. Experimental results on benchmark circuits show that the average accuracy of this approach is 0.9634 with Monte Carlo (MC) as the reference and it is 3445 times faster than the MC on average while its average memory cost is 1.67 greater than the MC model. Although the fitness of the worst input vector obtained by other reference methods is 1.09 times better than that of this approach on average, this approach is approximately 21 times faster than that reference method on average.

Proposal of a reliable embedded circuit to control a stepper motor using microblaze soft-core processor

The vast majority of embedded system designs start with a processor-based system, using a microcontroller or microprocessor as the core element to predict and process the basic control tasks. This paper aims to increase the reliability of controlling a stepper motor by an embedded circuit, which generates four digital signals of pulse width modulation (PWM). The manager of this circuit is an embedded processor licensed from Microblaze, which sits within the FPGA architecture Virtex 5. This processor analyzes the parameters to execute the rotation under the best conditions (energy consumption, speed, precision, reliability). The communication with the PC takes place via the RS232 link to provide feedback. The autonomous processor generates an independent control frequency of the PC. The four digital signals of PWM are simulated on Xilinx's ISim interface and sent to the ULN2803 amplifier circuit to run the stepper motor.

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated for advanced technology nodes, where transistor dimensions reach atomic levels and established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static timing analysis (STA) equips designers with accurate statistical delay distributions. Timing guardbands that are small, yet sufficient, can then be effectively estimated. However, such analysis is costly as it requires intensive Monte-Carlo simulations. Further, it necessitates access to confidential physics-based aging models to generate the standard-cell libraries required for STA. In this work, we employ graph neural networks (GNNs) to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit. Our proposed GNN4REL framework empowers designers to perform rapid and accurate reliability estimations without accessing transistor models, standard-cell libraries, or even STA; these components are all incorporated into the GNN model via training by the foundry. Specifically, GNN4REL is trained on a FinFET technology model that is calibrated against industrial 14-nm measurement data. Through our extensive experiments on EPFL and ITC-99 benchmarks, as well as RISC-V processors, we successfully estimate delay degradations of all paths—notably within seconds—with a mean absolute error down to 0.01 percentage points.

An efficient capuchin search algorithm for extracting the parameters of different PV cells/modules

Constructing an equivalent circuit for the photovoltaic (PV) generating unit converging the real operation is a difficult process because of unavailability of some parameters. Many approaches have been conducted in this field; however, they have some problems in computational time and are stuck in local optima. Therefore, this study proposes a simple, robust, and efficient methodology-incorporated capuchin search algorithm (CapSA) to construct the equivalent circuit of the PV generating unit via identifying its parameters. The CapSA is selected as it is simple and requires less computational time in addition to exploration/exploitation balance that avoids local optima. The process is formulated as an optimization problem, which aims at minimizing the root mean square error (RMSE) between measured and simulated currents. A single-diode model (SDM), double-diode model (DDM), and three-diode model (TDM) of different PV cells and panels operating at either constant or variable weather conditions are constructed. A comparison to different programmed metaheuristic approaches is conducted. The best RMSE values obtained by the proposed CapSA are 2.27804E-04, 1.3808E-04, and 1.5182E-04 for SDM, DDM, and TDM of PVW 752 cell, respectively. For the KC200GT panel, the proposed approach achieved the best fitness values of 3.4440E-04, 1.5617E-03, and 6.6008E-03 at 25°C, 50°C, and 75°C, respectively. The obtained results confirmed the superiority and competence of the proposed CapSA in constructing a reliable equivalent circuit for the PV cell/panel.

A Study on Over-Molded Copper-Based Flexible Electronic Circuits.

Over-molding has been proposed in recent years as an integrated functional flexible circuit board in a plastic part. This method uses the conventional process for film insert technology. Over-molding has attracted significant attention across many industries due to its potential to deliver different electrical functions in a variety of different part geometries, especially in automotive interiors and home appliances. While it has great application potential, manufacturing challenges continue throughout foil fabrication and injection molding. This raises challenges for designers and researchers responsible for maintaining the reliability of such electronic flexible circuits. Therefore, the purpose of this research paper is to improve some of the over-molding process parameters. On 0805 and 1206 over-molded zero-ohm resistors, electrical, mechanical, and failure characterization was performed. Those components were mounted in parallel, perpendicular, and 45° angled arrangements on two different polymer substrates, polyimide (PI) and polyethylene terephthalate (PET) using lead-free solder, low-melt solder, and conductive adhesive paste. Moreover, as an over-molding material, polycarbonate (PC) with medium viscosity was used. The effect of using different mold shapes (corner mold, 2 mm flat mold, and 3 mm flat mold) and injection molding process parameters (injection speeds and melt temperature) was studied.

Comprehensive physics-based RRAM compact model including the effect of variability and multi-level random telegraph noise

Resistive Random Access Memory (RRAM) technologies are a promising candidate for the development of more energy efficient circuits, for computing, security, and storage applications. However, such devices show stochastic behaviours that not only originate from variations introduced during fabrication, but that are intrinsic to their operation. Specifically, cycle-to-cycle variations cause the programmed resistive state to be randomly distributed, while Random Telegraph Noise (RTN) introduces random current fluctuations over time. These phenomena can easily affect the reliability and performance of RRAM-based circuits. Therefore, designing such circuits requires accurate compact models. Although several RRAM compact models have been proposed in the literature, these are rarely implemented following the programming best-practice for improving the simulator convergence, and a compact model that is able to reproduce the device characteristic including thermal effects, RTN, and variability in multiple operating conditions using a single set of parameters is still missing. Also, only a few works in the literature describe the procedure to calibrate such compact models, and even fewer address the calibration of the variability on experimental data. In this work, we extend the UniMORE RRAM physics-based compact model by developing and validating two variability models, (i) a comprehensive variability model which can reproduce the effect of cycle-to-cycle variability in multiple operating conditions, and (ii) a simplified version that requires fewer calibration data and enables to reproduce cycle-to-cycle variations in specific operating conditions. The model is implemented following Verilog-A programming best-practices and validated on data from three RRAM technologies from the literature and experimentally on TiN/Ti/HfOx/TiN devices, and the relation between experimental data and the variability model parameters is described.

A general approach for degradation modeling to enable a widespread use of aging simulations in IC design

The importance of integrated circuit (IC) reliability has been growing to benefit from the potentials of advanced semiconductor technologies in long-living applications, such as automotive electronics. Today, prototypes and products are tested for their reliability. The most important procedures are summarized in the industry standard AEC-Q100 for automotive ICs. There are indications that these tests will not be sufficient for future applications so that simulation-based reliability assessments are expected to complement them soon. Circuit-level aging simulations are one approach to virtually investigate the IC reliability before entering manufacturing. Although they have been available for years, they still appear rarely used. Despite significant progress in research and industry, degradation modeling and validation of aging simulations are still demanding and need improvements. This article focuses on degradation modeling and outlines challenges as well as a solution approach to establish aging simulations as a widespread verification step in future IC design projects.

Energy balance and synchronization via inductive-coupling in functional neural circuits

A reliable functional neural circuit can estimate the information encoding and signal exchange between neurons, and thus the recognition of electric activities in biological issues can be considered with problems on functional networks connected by neural circuits because more biophysical factors can be taken into account. Neurons communicate with each other via synaptic connections, besides the electric synapse connection via resistor coupling, inductor is effective to perform function as chemical synapses by activating similar inductive field coupling. In this paper, two kinds of neural circuits (light-sensitive and thermosensitive circuits) are connected by an induction coil, and external stimuli are applied to detect the adaptive synchronization approach when the coupling intensity is controlled by energy diversity between neurons. The two neurons hold different intrinsic energy values and then the synaptic connection is created for fast energy exchange along the coupling channel with increasing coupling intensity adaptively. When the energy of two neural circuits/neurons reaches perfect balance, the coupling intensity terminates its further increase and maintains a constant value. In case of phase synchronization/lock between neurons, desynchronization occurs accompanied by continuous energy pumping along the coupling channel without energy balance. Indeed, external energy injection can enhance the field coupling between neurons for decreasing the energy diversity. The involvement of memristive function as induction current for discerning electromagnetic induction in one neuron can increase the energy diversity between neurons, and then bursting synchronization can be suppressed. For the same and identical neural circuits, adaptive growth of synaptic connection can realize perfect energy balance and complete synchronization. For different neural circuits, synchronization is corrupted even the field coupling is further enhanced in the intensity. As a result changeable energy diversity is helpful to induce desynchronization and potential neural disorders and diseases can be blocked.

Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

As CMOS devices become smaller, aging-induced and process variations become major issues for circuit reliability. In this paper, a statistical gate sizing method is proposed to improve the lifetime reliability of manufactured chips in the presence of process variations and aging effects. To this end, we propose a canonical first order delay model to estimate the delay degradation of a gate under negative bias temperature instability and process variations considering spatial correlations. Using the proposed gate delay model, a statistical static timing analysis method is introduced to compute the circuit delay considering the joint effect of process variation and negative bias temperature instability. To guarantee that the circuit meets the required timing constraints, we propose an incremental gate sizing technique. This technique first computes the criticality of each gate defined as the probability that a gate lies on the critical path due to negative bias temperature instability and process variations. Then, a group of gates with the highest ranking according to criticality is chosen for a gate sizing-based timing optimization. It is worth nothing that, by using the proposed statistical gate delay model, we can compute the criticality of each gate incrementally. Experimental results based on ISCAS’85 benchmark circuits show that the proposed method can improve the lifetime reliability defined as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1(\mu + 3\sigma)$ </tex-math></inline-formula> of the initial delay distribution of the circuit at the expense of 8.64% area overhead. In comparison with the path-based method, the proposed approach is much faster, especially for larger circuits, which makes it a viable solution to optimize the lifetime reliability of very large-scale circuits used in industry.

Characterization and optimization of active negative voltage driving circuit for CoolGaN HEMTs in a phase-leg configuration

The high switching speed of GaN HEMT will cause serious crosstalk in the phase-leg configuration. The negative turn-off driving voltage is usually recommended to avoid the parasitic shoot-through. However, the adoption of negative turn-off voltage will increase the reverse conduction loss during the dead time, which brings impact on the efficiency of GaN-based converter, and the selection of negative turn-off voltage is also limited by the maximum negative voltage capability of gate–source. Taking CoolGaN HEMT drive circuit as the research object, the crosstalk suppression method is analyzed in detail. Then, an active negative voltage driving circuit is proposed. The novel driving circuit realizes the negative-voltage and zero-voltage combined shutdown mode, which can not only meet the requirements of crosstalk suppression, but also minimize the reverse conduction loss of GaN device. The influence of crucial parameters in active negative voltage driving circuit on the reliability and power loss of bridge-arm circuit is explored, and the optimization design method of each parameter is obtained, so as to provide theoretical and design guidance for high efficiency driving circuit with high reliability.

A hybrid method for signal probability and reliability estimation with combinational circuits

Today's high-density integrated circuits (ICs) have become more sensitive to temperature, process variations and environmental noises. This makes their reliability evaluation one of critical issues in the design flow. Circuit reliability evaluation generally requires estimation of error-free signal probabilities and signal reliability correlations. In this paper, we present a fast hybrid method to estimate both signal probability and reliability simultaneously by using combination of analysis and statistical simulation. Simulation results show that the proposed method is hundreds of times faster than Monte-Carlo simulation, while maintaining a high level of accuracy.

A Critical Review on Reliability and Short Circuit Robustness of Silicon Carbide Power MOSFETs

A Critical Review on Reliability and Short Circuit Robustness of Silicon Carbide Power MOSFETs