Refresh Operations Research Articles

High-sensitivity UV phototransistor with GaN/AlGaN/GaN gate epi-structure

A highly sensitive UV phototransistor was developed using AlGaN/GaN heterojunction field effect transistor (HFET) technology. The phototransistor consisted of a thin undoped GaN layer added on top of a conventional AlGaN/GaN HFET structure. In such a structure, holes generated in the surface i-GaN layer are accumulated at the GaN/AlGaN interface, and they modulate the electrons in the FET channel. Due to this charge modulation effect, high photocurrent can be obtained. In the structure under study, hole life time was so long that a hole-evacuating refresh operation was required for fast response and linear sensitivity. When irradiated with UV light of 360 nm, a device with 6 × 10–4 mm2 active area produced two hundred times higher photocurrent than a commercial Si UV diode with a much larger area. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Capacitorless 1T DRAM Sensing Scheme With Automatic Reference Generation

To perform a current sensing in capacitorless 1-transistor (1T) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state "1", the data retention time in the holding mode is maximized. The proposed scheme is evaluated in a 2-kb test chip implemented in a 1-/spl mu/m partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 ns.

Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.

Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

A novel bitline sensing scheme is proposed for low-voltage DRAM to achieve low power dissipation and compatibility with low-voltage CMOS. One of the major obstacles in low-voltage DRAM is the degradation of data-retention time due to low signal level at the memory cell, which requires power-consuming refresh operations more frequently. This paper proposes an offset-cancellation sense-amplifier scheme (OCSA) that improves data-retention time significantly even at low supply voltage. It also improves die efficiency, because the proposed scheme reduces the number of sense amplifiers by supporting more cells in each sense amplifier. Measurements show that the data-retention time of the proposed scheme at 1.5-V supply voltage is 2.4 times of the conventional scheme at 2.0 V.

Efficient online and offline testing of embedded DRAMs

This paper presents an integrated approach for both built-in online and off-line testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during off-line test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection. Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

Analysis of the Use of Molecular Resonant Tunneling Diodes for Local Refresh of Dynamic Random Access Memory Cells

ABSTRACTSimulations have been made to analyze the use of molecular resonant tunneling diodes for local refresh of DRAM (Dynamic Random Access Memory) cells. Local refresh can be provided by a latch consisting of a pair of resonant tunneling diodes connected to the storage capacitor of the cell. Such a solution would significantly reduce the standby power consumption of the DRAM cell. We have compared the requirements on the resonant tunneling diodes for proper refresh operation with the electrical properties of published molecules with resonant IV-curves. The simulations show that no molecules with resonant electrical properties published so far in the literature have properties making them useful for this particular application. This is true also for low temperature operation. The issues of maximum tolerable series resistance and of maximum tolerable fluctuations in the number of attached molecules have also been addressed. Our results show that the focus for development of molecules with resonant electrical properties should be to find molecules with resonance for lower applied voltages and lower current levels than the molecules published so far. If the synthesis of new molecules with attractive properties is successful the merging of silicon technology and molecular electronics, for instance for new generations of DRAM cells, is a realistic future path of microelectronics.

High-density chain ferroelectric random access memory (chain FRAM)

A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F/sup 2/ size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V/sub dd/ cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation.

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced.

A mechanism and a reduction technique for large reverse leakage current in p-n junctions

The origin of anomalously large p-n junction leakage current in Si is investigated. The leakage has strong electric field dependence and weak temperature dependence, and therefore cannot be explained by either generation-recombination current or diffusion current. It may be explained by the local Zener effect at local enhancement of the electric field around small precipitates in the depletion layer. Supposing a spherical precipitate, the electric field will be enhanced as much as 1.3 times for a SiO/sub 2/ precipitate and 3 times for a metal precipitate. The leakage features are explained by the electric field dependence and the temperature dependence of the local Zener probability. A new approach to reduce the local Zener probability by controlling the profile of the electric field is proposed, and the validity of the approach is confirmed by direct experiment and by improvement in the refresh operation of DRAM cells. >

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 /spl mu/m technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells. >

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.

A 64Kbit MOS dynamic RAM with auto/self refresh functions

AbstractUntil now, a refresh operation, which is necessary in using MOS dynamic RAMs, has made MOS dynamic RAMs more difficult to use compared with static RAMs. On the other hand, with advances in MOS dynamic RAMs, new refresh modes, i.e., automatic and self refresh modes, become available when a spare pin is applied to a refresh control signal. In 64Kbit MOS dynamic RAMs, pin 1 can be such a refresh control terminal if the substrate bias is generated on‐chip. Circuit considerations in accommodating the automatic and self refresh modes by pin 1 are discussed, with special attention given to the on‐chip refresh address counter and the timer used during the self refresh. A practical 64Kbit MOS dynamic RAM has been realized with the chip area increase of 1.6% and the standby current increase of 0.3 mA as the result of implementing the automatic and self refresh modes.

Multilevel random-access memory using one transistor per cell

A memory cell capable of storing multilevel or analog information and providing random-access operation with nondestructive readout has been studied. It uses a single junction field-effect transistor (JFET) as the storage cell. Experimental and analytical studies suggest that eight of sixteen level operation should be feasible with refresh operations every 0.1 to 1 s; cell area can be under 2 mil/SUP 2/. Tracking voltage and current reference circuitry is used to accommodate variations in fabrication processing and operating temperature.