Abstract
To perform a current sensing in capacitorless 1-transistor (1T) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state "1", the data retention time in the holding mode is maximized. The proposed scheme is evaluated in a 2-kb test chip implemented in a 1-/spl mu/m partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 ns.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.