Redundant CORDIC Research Articles

A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation.

Bio-inspired neuron models are the key building blocks of brain-like neural networks for brain-science exploration and neuromorphic engineering applications. The efficient hardware design of bio-inspired neuron models is one of the challenges to implement brain-like neural networks, as the balancing of model accuracy, energy consumption and hardware cost is very challenging. This paper proposes a high-accuracy and energy-efficient Fast-Convergence COordinate Rotation DIgital Computer (FC-CORDIC) based Izhikevich neuron design. For ensuring the model accuracy, an error propagation model of the Izhikevich neuron is presented for systematic error analysis and effective error reduction. Parameter-Tuning Error Compensation (PTEC) method and Bitwidth-Extension Error Suppression (BEES) method are proposed to reduce the error of Izhikevich neuron design effectively. In addition, by utilizing the FC-CORDIC instead of conventional CORDIC for square calculation in the Izhikevich model, the redundant CORDIC iterations are removed and therefore, both the accumulated errors and required computation are effectively reduced, which significantly improve the accuracy and energy efficiency. An optimized fixed-point design of FC-CORDIC is also proposed to save hardware overhead while ensuring the accuracy. FPGA implementation results exhibit that the proposed Izhikevich neuron design can achieve high accuracy and energy efficiency with an acceptable hardware overhead, among the state-of-the-art designs.

No-overflowing Magnification Scheme in Redundant CORDIC algorithm and its implementation in FPGA

In this paper, normalization and magnification methods to maintain the calculating accuracy of CORDIC algorithm for small amplitude inputs are discussed, especially the overflowing boundaries are analyzed through mathematical deduction and the correctness has been proven by simulation. Finally, the FPGA implementations of different methods are conducted, which shows that the proposed magnification factor chosen scheme has an effective reduction on hardware resources consumption compared with the conventional normalization method.

Redundant Floating-Point Decimal CORDIC Algorithm

In this work, we propose a new decimal redundant CORDIC algorithm to manage transcendental functions, using floating-point representation. The algorithms determine the direction of the elementary rotation using sign estimations. Unlike binary redundant CORDIC, repetition of iterations are not required to ensure convergence since novel decimal codes have been carefully selected with sufficient redundancy to prevent any repetition. The algorithms are mapped to a low-cost unit based on a decimal 3-2 carry-save adder which can also be used as a floating-point decimal division unit. Compared to current decimal floating-point units, the implementation of our algorithm involves minor modifications of the native hardware, while providing a huge set of elementary functions.

A new semi-flat architecture for high speed and reduced area CORDIC chip

In this contribution we present a new CORDIC architecture called ‘semi-flat’ which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.

Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC andIts Application to Complex SVD

Redundant Implementations of Multi-dimensional CORDIC algorithms are presented where the carry-ripple additions are replaced by carry-free signed-digit additions. Both folded (iterative) and unfolded (pipelined) architectures are considered in the redundant implementation. Furthermore, the scaling iterations are merged with the unscaled CORDIC iterations in the folded CORDIC architecture in order to reduce the overall computation time of one CORDIC operation. The redundant multidimensional CORDIC is then applied to the singular value decomposition of complex matrices, with either a folded or an on-line architecture. The resulting processing speed is higher than with alternative approaches based on 2-D CORDIC.

Beyond-Binary Arithmetic: Algorithms and VLSI Implementations.

Beyond-binary arithmetic algorithms are defined as a new class of computer arithmetic algorithms which employ non-binary data representations to achieve higher performances beyond those of conventional binary algorithms. This paper presents prominent examples of beyond-binary arithmetic algorithms: examples include (i) a high-radix redundant division algorithm without using lookup tables, (ii) a high-radix redundant CORDIC algorithm for fast vector rotation, and (iii) redundant complex arithmetic algorithms for fast real/complex-mixed computations.

Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure

A new high-speed redundant CORDIC processor is designed and implemented based on the double rotation method, which turns out to be the two-dimensional (2D) Householder CORDIC, a special case of the generalized Householder CORDIC in the 2D Euclidean vector space. The new processor has the advantages of regular structure and high throughput rate. The pipelined structure with radix-2 signed-digit (SD) redundant arithmetic is adopted to reduce the carry-propagation delay of the adders while the digit-serial structure alleviates the burden of the hardware cost and I/O requirement. Compared to previously proposed designs, the new CORDIC processor preserves the constant scaling factor, an important merit of the original CORDIC, and thus does not require any complicated division or square-root operations for variable scaling factor calculation. Furthermore, the processor is well suited to VLSI implementation since it does not call for any irregularly inserted correcting iterations. Both angle calculation mode for computing trigonometric function and vector rotation mode for plane rotations are supported. Practical VLSI chip implementation of the fixed-point redundant CORDIC processor using 0.6 μm standard cell library is given including detailed numerical error analysis.

A novel implementation of CORDIC algorithm using backward angle recoding (BAR)

We propose a backward angle recoding (BAR) method to eliminate redundant CORDIC elementary rotations and hence expedite the CORDIC rotation computation. We prove that for each of the linear, circular, and hyperbolic CORDIC rotations, the use of BAR guarantees more than 50% reduction of elementary CORDIC rotations provided the scaling factor needs not be kept constant. The proposed BAR algorithm is simple, and amenable to VLSI implementation. Taking practical applications into consideration, we discuss how to incorporate convergence range enhancement procedure with BAR, and how easy it is to devise a constant-scaling-factor BAR algorithm while still enjoying 25% reduction of CORDIC elementary rotations.

Redundant and on-line CORDIC for unitary transformations

Two-sided unitary transformations of arbitrary 2/spl times/2 matrices are needed in parallel algorithms based on Jacobi-like methods for eigenvalue and singular value decompositions of complex matrices. This paper presents a two-sided unitary transformation structured to facilitate the integrated evaluation of parameters and application of the typically required transformations using only the primitives afforded by CORDIC; thus enabling significant speedup in the computation of these transformations on special-purpose processor array architectures implementing Jacobi-like algorithms. We discuss implementation in (nonredundant) CORDIC to motivate and lead up to implementation in the redundant and on-line enhancements to CORDIC. Both variable and constant scale factor redundant (CFR) CORDIC approaches are detailed and it is shown that the transformations may be computed in 10n+/spl delta/ time, where n is the data precision in bits and /spl delta/ is a constant accounting for accumulated on-line delays. A more area-intensive approach using a novel on-line CORDIC encoded angle summation/difference scheme reduces computation time to 6n+/spl delta/. The area/time complexities involved in the various approaches are detailed. >

Constant-factor redundant CORDIC for angle calculation and rotation

A constant-factor redundant-CORDIC (CFR-CORDIC) scheme, where the scale factor is kept constant while an angle for plane rotations is computed, is developed. The direction of rotation is determined from an estimate of the sign, and convergence is assured by suitably placed correcting iterations. The number of iterations in the CORDIC rotation unit is reduced by about 25% by expressing the direction of the rotation in radix-2 and radix-4, and conversion to conventional representation is done on the fly. The performance of CFR-CORDIC is estimated and compared with that of previously proposed schemes. It is found to provide an execution time similar to that of redundant CORDIC with a variable scaling factor, with a significant saving in area. >

A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms

As CORDIC algorithms attract more and more attention in elementary function evaluation and signal processing applications, the problem of their VLSI realization has drawn considerable interest. In this work we present speed enhancement techniques for these types of algorithms, covering algorithmic and implementation issues. We discuss speed limiting issues, namely addition techniques, appropriate number systems and scaling factor compensation with special emphasis on low latency time. A new carry-select adder structure will be presented that offers an excellent tradeoff between speed and VLSI chip area. With two scaling factor compensation schemes the fastest or most area economical CORDIC implementations are feasible. Also, the close relationship between SRT division and the new redundant CORDIC algorithms will be demonstrated.

Redundant and on-line CORDIC: application to matrix triangularization and SVD

Several modifications to the CORDIC method of computing angles and performing rotations are presented: (1) the use of redundant (carry-free) addition instead of a conventional (carry-propagate) one; (2) a representation of angles in a decomposed form to reduce area and communication bandwidth; (3) the use of on-line addition (left-to-right, digit-serial addition) to replace shifters by delays; and (4) the use of online multiplication, square root, and division to compute scaling factors and perform the scaling operations. The modifications improve the speed and the area of CORDIC implementations. The proposed scheme uses efficiently floating-point representations. The application of the modified CORDIC method to matrix triangularization by Givens' rotations and to the computation of the singular value decomposition (SVD) are discussed. >