Abstract
As CORDIC algorithms attract more and more attention in elementary function evaluation and signal processing applications, the problem of their VLSI realization has drawn considerable interest. In this work we present speed enhancement techniques for these types of algorithms, covering algorithmic and implementation issues. We discuss speed limiting issues, namely addition techniques, appropriate number systems and scaling factor compensation with special emphasis on low latency time. A new carry-select adder structure will be presented that offers an excellent tradeoff between speed and VLSI chip area. With two scaling factor compensation schemes the fastest or most area economical CORDIC implementations are feasible. Also, the close relationship between SRT division and the new redundant CORDIC algorithms will be demonstrated.
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