Abstract
Jack Edward Volder had introduced the CORDIC (COordinate Rotation DIgital Computer) in 1959. This year, critical development and advancement of the CORDIC algorithm have reached 62 years. The VLSI implementation of the CORDIC requires simple hardware (of the form add–shift), which makes CORDIC the most suitable building block for many real-time applications. The sequential nature of the CORDIC computation and scale factor are crucial aspects to be considered as they limit the overall performance of the algorithm. In this work, we have studied the various CORDIC algorithms and their architectures which improve the performance of the standard radix-2 CORDIC algorithm. This comparative study aims to provide first-order information on CORDIC algorithm implementations, including their potential applications. In addition, the study also reflected the works done by numerous researchers and highlighted the limitations of the existing architectures and algorithms, and executed the assessment using various parameters such as convergence range, number of iterations required to achieve the complete rotation, and hardware resource complexity to implement [Formula: see text]/[Formula: see text] rotator, [Formula: see text] rotator, and scale factor compensation. We have also carried out error analysis of various CORDIC algorithms in terms of root-mean-squared error (RMSE) and peak signal-to-noise ratio (PSNR). The number of iterations, scale factor, and the sequential computing of the micro-rotations can be identified as significant improvement areas of the CORDIC algorithm and modifications are required for real-time applications.
Published Version
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