Reduction Of Threading Dislocation Density Research Articles

Capturing the Effects of Free Surfaces on Threading Dislocation Density Reduction

The big concern with using silicon as a substrate for making Ge and III-V devices is the dislocation density in the epilayers. Dislocations degrade device performance by trapping the photo-generated carriers, dragging down efficiency.In this presentation, we show that dislocation engineering using nanovoids in the heteroepitaxy of Ge/Si can be a plausible path for monolithic integration of high-quality GaAs on Si platform. Possible mechanisms responsible for threading dislocation (TD) density reduction through free surfaces located, either in the Ge layer or in Si substrate that lead to their annihilation or fusion are discussed. By combining various scanning and transmission electron microscopy techniques, it has been possible to link different effects of either of the free wedge surfaces on dislocation, particularly, threading arm pinning by nanovoids. The results suggest that introducing nanovoids favors recombination of TDs by increasing the characteristic interaction distance between neighboring dislocations. In fact, the creation of free surfaces could facilitate interactions between dislocations, enabling the dislocation network to change its connectivity in a way, which facilitates the subsequent annihilation of TD segments. In addition, the voids formed in the silicon substrate could potentially capture and thereby combine many more TDs. The TDs bend towards the voids in Si in order to minimize their length, causing their recombination and elimination at the nearest free surface thus leading to the creation of an almost defect-free Ge layer on Si [1].The use of such a simple, industry friendly, inexpensive and self-organised process through electrochemical etching and thermal annealing could be crucial in cutting manufacturing costs and enabling market penetration of III–V on Si-based devices.[1] Y. A. Bioud et al., “Uprooting defects to enable high-performance III–V optoelectronic devices on silicon,” Nat. Commun., vol. 10, no. 1, 2019.

Capturing the Effects of Free Surfaces on Threading Dislocation Density Reduction

The big concern with using silicon as a substrate for making Ge and III-V devices is the dislocation density in the epilayers. Dislocations degrade device performance by trapping the photo-generated carriers, dragging down efficiency. In this manuscript, a Ge/Si substrate is treated with a post epitaxial process to create a region with a high density of nanovoids within the Ge/Si structure, which acts as a free surface that attracts dislocations, facilitating the subsequent annihilation of their threading arms. Nanovoids are formed in the Ge layer by electrochemical porosification, followed by thermal annealing, creating a new configuration referred to as nanovoid-based Ge/Si virtual substrate (NVS).

Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice

The influence of introducing a SiGe / Ge superlattice (SL) between Ge layers and Si substrate for the sake of the reduction of the threading dislocation density (TDD) without additional annealing is investigated. In the case of 2.8 μm thick Ge directly grown on Si, the TDD at the surface is 7.6×10-8 cm-2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8 / Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8 / Ge, the TDD is reduced to 7.1×10-8, 5.9×10,-8 and 5.3×10-8 cm-2, respectively. The lateral lattice parameters of these SLs are ~5.656Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation (MD) formation. Further TDD reduction is realized with increasing Si concentration in the SiGe / Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8×10-8 cm-2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.

Optical and interfacial properties of epitaxially fused GaInP/Si heterojunction

This work investigates the optical and interfacial properties of epitaxially fused direct GaInP/Si heterojunctions realized by the corrugated epitaxial lateral overgrowth (CELOG) approach. To provide a broad analysis of the above heterojunction, photoluminescence (PL), cathodoluminescence (CL), Raman, and high-resolution transmission electron microscopy (TEM) were employed in this study. The enhanced luminescence intensity was observed in the direct GaInP/Si heterojunction in the cross-sectional CL because of the reduced defect density in the CELOG GaInP. The spatial resolution dependent PL and CL spectra of GaInP on Si yielded the composition variation of GaInP arising from the anisotropic growth behavior of CELOG. The Ga composition, x, in GaxIn1−xP/Si at the interface deduced from the lattice constant measured by TEM has a good agreement with the results of PL and CL. Low thermal and lattice mismatch strain in CELOG GaInP on Si were revealed by the Raman spectra. TEM investigation further revealed the atomic structure of some planar defects in CELOG GaInP over Si. It is confirmed that although a thin atomic disorder was observed on the surface of Si substrate, an epitaxially fused GaInP/Si heterojunction with a reduced threading dislocation density of ∼6.4 × 107 cm−2 in comparison to ∼4.8 × 108 cm−2 in the InP seed on Si has been successfully fabricated by the CELOG technique despite about 4% lattice mismatch between GaInP and Si. The findings of this study demonstrate the great potential of the CELOG technique for promoting monolithic integration of III-V/Si-based optoelectronics.

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon.

Reduction of threading dislocation density (TDD) in epitaxial germanium (Ge) on silicon (Si) has been one of the most important challenges for the realization of monolithically integrated photonics circuits. The present paper describes methods of theoretical calculation and experimental verification of a novel model for the reduction of TDD. The method of theoretical calculation describes the bending of threading dislocations (TDs) based on the interaction of TDs and non-planar growth surfaces of selective epitaxial growth (SEG) in terms of dislocation image force. The calculation reveals that the presence of voids on SiO2 masks help to reduce TDD. Experimental verification is described by germanium (Ge) SEG, using an ultra-high vacuum chemical vapor deposition method and TD observations of the grown Ge via etching and cross-sectional transmission electron microscope (TEM). It is strongly suggested that the TDD reduction would be due to the presence of semicylindrical voids over the SiO2 SEG masks and growth temperature. For experimental verification, epitaxial Ge layers with semicylindrical voids are formed as the result of SEG of Ge layers and their coalescence. The experimentally obtained TDDs reproduce the calculated TDDs based on the theoretical model. Cross-sectional TEM observations reveal that both the termination and generation of TDs occur at semicylindrical voids. Plan-view TEM observations reveal a unique behavior of TDs in Ge with semicylindrical voids (i.e., TDs are bent to be parallel to the SEG masks and the Si substrate).

An Increase of Threading Dislocations Filtering Efficiency in Al2O3 Templates with Faceted Surface Morphology During a Growth by Molecular Beam Epitaxy

We present the results of a transmission electron microscopy and X-ray diffractometry investigation of AlN/c-Al2O3 templates with GaN ultrathin insertions grown by plasma-assisted molecular beam epitaxy. It has been shown that AlN buffer layers with faceted surface morphology provide a greater threading dislocation density reduction than smooth layers. The filtering effect of GaN ultrathin insertions has been confirmed.

ПЭМ-исследование многослойных буферных структур AlN-AlGaN-GaN на кремниевых подложках

By transmission electron microscopy are studied two buffer structures based on AlGaN alloys doped with silicon and don't. The structures were grown on (111) orientated Si substrates by metal-organic vapour-phase epitaxy with consistently decreasing Al content. It is found that noticeable threading dislocation density reduction took place in intermediate layers at changing Al concentration from 32 to 23%. A phase decay and a composition modulation in growth direction in AlGaN layers with Al content 32, 23, 12 and 4% are observed. A model of the layers structure in the composition modulation area is proposed.

Boosted ultraviolet electroluminescence of InGaN/AlGaN quantum structures grown on high-index contrast patterned sapphire with silica array

Epitaxially grown high crystalline quality InGaN/AlGaN multiple quantum structures on patterned sapphire with silica array (PSSA) have been successfully demonstrated. In comparison to conventional epilayers grown on patterned sapphire substrate (PSS), we observed a reduced threading dislocation density in the films grown on PSSA, attributing to the preferable vertical growth mode and reduced misfit at the coalescence boundary. Furthermore, a significant enhancement in light extraction efficiency can be achieved from InGaN/AlGaN-based ultraviolet light-emitting diodes (UVLEDs) built on PSSA owing to the large refractive index contrast between the epilayers and PSSA. More photons can escape from the top and bottom of the device, which was confirmed by numerically modeling light propagation within such device architecture. Benefiting from the reduced threading dislocation density and enhanced light extraction efficiency, the external quantum efficiency (EQE) of the fabricated UVLEDs on PSSA was more than two times higher than that of devices on the conventional flat sapphire substrate and it was additionally enhanced by 26.1% in comparison to the devices fabricated on PSS under an injection current of 150 mA. Therefore, the successful demonstration of UVLED on PSSA provides an unprecedented opportunity in achieving higher electroluminescence performance in future solid-state UV light sources.

LT-AlSb Interlayer as a Filter of Threading Dislocations in GaSb Grown on (001) GaAs Substrate Using MBE

We report on the role of AlSb material in the reduction of threading dislocation density (TDD) in the GaSb/AlSb/GaAs system. The AlSb layers were grown using low-temperature (LT) MBE, exploiting the interfacial misfit (IMF) dislocation array. AlSb layers with four different thicknesses in the range of 1–30 nm were investigated. The results showed the inhibiting role of LT-AlSb layers in the reduction of TDD. Values of TDD as low as 2.2 × 106 and 6.3 × 106 cm−2 for samples with thin and thick AlSb layers were obtained, respectively. The filtering role of AlSb material was proven despite the IMF-AlSb/GaAs interface’s imperfectness caused by the disturbance of a 90° dislocation periodic array by, most likely, 60° dislocations. The dislocation lines confined to the region of AlSb material were visible in HRTEM images. The highest crystal quality and smoother surface of 1.0 μm GaSb material were obtained using 9 nm thick AlSb interlayer. Unexpectedly, the comparative analysis of the results obtained for the GaSb/LT-AlSb/GaAs heterostructure and our best results for the GaSb/GaAs system showed that the latter can achieve both higher crystal quality and lower dislocation density.

Low-Threshold Epitaxially Grown 1.3-μm InAs Quantum Dot Lasers on Patterned (001) Si

A three-fold reduction of threshold current, with a minimum threshold current density of 286 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a maximum operating temperature of 80 °C, and a maximum 3-dB bandwidth of 5.8 GHz was achieved for 1.3- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m InAs quantum dot lasers on patterned, on-axis (001) Si. This was enabled by the reduced threading dislocation density (from 7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> to 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> ), and optimized probe design. The patterned Si produced antiphase domain free material in the coalesced GaAs buffer layer with reduced misfit/threading dislocation nucleation, without the use of Ge/GaP buffers or substrate miscut. Utilizing aspect ratio trapping, cyclic thermal annealing, and dislocation filter layers, high-quality III–V on Si devices were grown, demonstrating the compelling advantages of this patterned Si template for a monolithic Si photonics integration platform.

Influence of Annealing Condition on Threading Dislocation Density of Ge Grown by RPCVD

The influence of annealing conditions on the crystallinity of Ge deposited on Si (001) is investigated. Ge deposited with postannealing at 800°C or 850°C, five cycles of postannealing at 750°C and 850°C and several cycles of annealing at 800°C or 850°C during the Ge growth by interrupting the deposition step (cyclic annealing) are compared. To check the threading dislocation density (TDD) of the deeper part of the Ge layer, thinning by HCl vapor phase etching (VPE) followed by Secco defect etching is performed for 5 µm thick Ge of all annealing variants. By comparing TDD of the same Ge thickness without / with HCl VPE, TDD reduction after VPE is observed for the samples with cyclic annealing process only. In the case of the cyclic annealing process, 5 µm thick Ge shows the same TDD level compared to that with five cycles of postannealing at 750°C and 850°C with lower thermal budget. A lower amount of tilted Ge planes at the interface is confirmed for the sample with cyclic annealing indicating higher crystal quality also in the deeper part of the Ge layer.

Comparative study of AlGaN/GaN heterostructures grown on different sapphire substrates

Abstract AlGaN/GaN heterostructures were grown on the conventional planar sapphire substrate (CSS), nano-scale patterned sapphire substrate (NPSS) and micro-scale patterned sapphire substrates (MPSS) by metal organic chemical vapor deposition respectively. The heterostructure grown on the MPSS has significantly lower threading dislocation density (TDD) than those grown on the NPSS and CSS. The bending and quenching of threading dislocations induced by lateral growth are the main factors for the reduction of TDD. Correspondingly, the carrier mobility of heterostructure grown on the MPSS is also the highest.

Optical and interface properties of direct InP/Si heterojunction formed by corrugated epitaxial lateral overgrowth

We fabricate and study direct InP/Si heterojunction by corrugated epitaxial lateral overgrowth (CELOG). The crystalline quality and depth-dependent charge carrier dynamics of InP/Si heterojunction are assessed by characterizing the cross-section of grown layer by low-temperature cathodoluminescence, time-resolved photoluminescence and transmission electron microscopy. Compared to the defective seed InP layer on Si, higher intensity band edge emission in cathodoluminescence spectra and enhanced carrier lifetime of InP are observed above the CELOG InP/Si interface despite large lattice mismatch, which are attributed to the reduced threading dislocation density realized by the CELOG method.

The substantial dislocation reduction by preferentially passivating etched defect pits in GaN epitaxial growth

We demonstrate the use of in situ SiNx preferentially deposited on the etched defect pits as a mask to block the propagation of threading dislocations (TDs). Etch pits are generated on the GaN template using the wet etching technique. The SiNx layer is then deposited on etch pits, followed by a regrown GaN layer. It turns out that a 60% reduction in TD density of the GaN epilayer is obtained compared with the conventional GaN growth method. The significant improvement is more attributed to the prevention effect by covering etch pits rather than the merging effect by reorienting the dislocation propagation.

New Relaxation Mechanism Enabling High-Quality, Laterally Grown Ge on Si

We demonstrate a novel growth technique, metal-catalyzed, lateral epitaxial growth, to grow Ge films laterally on Si with reduced threading dislocation densities (TDD). In contrast to traditional planar film growth on Si, this technique starts with a small crystal nucleation at a specific position on Si followed by Ge lateral film growth. In plan-view and cross-sectional transmission electron microscopy micrographs, high-density threading dislocations were found to be present in the initial growth areas, while the lateral overgrowth areas demonstrated substantially reduced TDD or even defect-free areas. Furthermore, the X-ray diffraction results showed that the films were fully relaxed and mostly pure Ge. Full relaxation and low TDD Ge films are two surprising results given that the growth occurred at a low temperature (375 °C), which cannot be understood with the current misfit dislocation nucleation and glide model of film relaxation. For these reasons, we suggest the presence of a new relaxation mechan...

Epitaxial lateral overgrowth of GaN on nano-cavity patterned sapphire substrates

The epitaxial lateral overgrowth of GaN by metal-organic chemical vapor deposition using a nano-cavity patterned sapphire substrate (NCPSS) was investigated. The NCPSS, with a hexagonal non-close-packed nano-cavity pattern on the sapphire substrate, was fabricated by polystyrene sphere coating and size reduction by reactive ion etching, followed by deposition of alumina and thermal oxidation. The coalescence of GaN on the NCPSS was achieved by the formation of relatively large GaN islands and enhanced lateral overgrowth of the GaN islands over several nano-cavity pattern areas. The threading dislocation density (TDD) measured by cathodoluminescence measurement was significantly reduced from 2.4 × 108 cm−2 to 6.9 × 107 cm−2 by using the NCPSS. A dislocation behavior that contributes to the reduction of TDD of the GaN layer was observed by transmission electron microscopy. Raman spectroscopy revealed that the compressive stress in the GaN layer was reduced by 21% due to the embedded nano-cavities. In addition, the diffuse reflectance of GaN on the NCPSS was enhanced by 54% ∼ 62%, which is attributed to the increased probability of light extraction through effective light scattering by nano-cavities.

Influence of annealing conditions on threading dislocation density in Ge deposited on Si by reduced pressure chemical vapor deposition

The influence of annealing conditions on the crystallinity of Ge deposited on Si(001) is investigated. Ge deposited with postannealing at 800 °C and 850 °C, five cycles of postannealing at 750 °C and 850 °C (temperature-swing postannealing) and several cycles of annealing at 800 °C or 850 °C during the Ge growth by interrupting the deposition step (cyclic annealing) are compared. To check the threading dislocation density (TDD) of the deeper part of the Ge, thinning by HCl vapor phase etching (VPE) followed by Secco defect etching is performed for 5 μm thick Ge of all three annealing variants. By comparing the TDD of the same Ge thickness with and without HCl VPE, TDD reduction by VPE is observed for the sample using the cyclic annealing process only. Lower TDD is observed at higher postannealing temperature. By the five cycles of temperature swinging, TDD becomes around a half compared to conventional postannealing at 850 °C. In the case of the cyclic annealing process significant improvement of TDD is observed with increasing Ge thickness. Even at a maximum temperature of 800 °C, the same or lower TDD levels were observed for higher than 2 μm thick Ge compared to that with five cycles of temperature-swing postannealing. For the sample with cyclic annealing at 800 °C, a lower Si diffusion length into Ge is also observed for the cyclic annealing process indicating a lower thermal budget. A lower amount of tilted Ge planes at the interface is confirmed showing higher crystal quality also in the deeper part of the Ge layer.

Thermophysics Simulation of Laser Recrystallization of High-Ge-Content SiGe on Si Substrate

The high-Ge-content SiGe material on the Si substrate can be applied not only to electronic devices but also to optical devices and is one of the focuses of research and development in the field. However, due to the 4.2% lattice mismatch between Si and Ge, the epitaxial growth of the high-Ge-content SiGe epitaxial layer directly on the Si substrate has a high defect density, which will seriously affect the subsequent device performance. Laser recrystallization technique is a fast and low-cost method to effectively reduce threading dislocation density (TDD) in epitaxial high-Ge-content SiGe films on Si. In this paper, by means of finite element numerical simulation, a 808 nm laser recrystallization thermal physics model of a high-Ge-content SiGe film (for example, Si0.2Ge0.8) on a Si substrate was established (temperature distribution physical model of Si0.2Ge0.8 epitaxial layer under different laser power, Si0.2Ge0.8 epitaxial layer thickness, and initial temperature). The results of this paper can provide important technical support for the preparation of high-quality high-Ge-content SiGe epilayers on Si substrates by laser recrystallization.

Design of a 1.55 µm nanoscale laser array on v-groove patterned Si substrates

A 1.55 µm nanoscale laser array is proposed and designed on v-groove patterned Si (0 0 1) substrates. The laser array is designed by taking full advantage of the periodic groove structures of the patterned substrates. The periodic groove structures separated by a SiO2 mask can effectively reduce threading dislocation density in the active region and provide a strong lateral optical confinement for the laser array structure. The optical mode distributions of the single laser are investigated in detail, and the optical confinement factor is calculated to optimize the structure parameters of the laser array. An optimal value of 9.3% for the optical confinement factor is obtained. The analysis of threshold conditions shows that the laser array can achieve lasing with a cavity length of about 1 mm for an internal loss of 40 cm−1.

Properties of AlN layers grown on c-sapphire substrate using ammonia assisted MBE

AlN epilayer properties (120 nm thick) grown by ammonia assisted molecular beam epitaxy on c-sapphire substrates with different low temperature AlN buffer layers (LT-BL) have been studied. The role of the LT-BL on the AlN structural and optical properties was investigated as a function of the LT-BL thickness and growth temperature. Optimum growth conditions were identified with LT-BL thickness of 3 nm and growth temperature between 480 °C and 520 °C. It was shown that by optimizing these conditions, a reduction of both mixed and edge threading dislocation densities up to 75% is achieved. The impact of the growth temperature of the AlN epilayer was also studied showing an additional improvement of the AlN crystal and morphological properties while growing at higher temperature. A correlation between the epilayer strain and the PL emission was also investigated. Finally, an Al0.7Ga0.3N:Si doped layer was grown on the top of the optimized AlN template showing a smooth surface with monoatomic steps and a roughness ∼0.2 nm, confirming the potential of such templates for the fabrication of AlGaN based heterostructures.