Reducing Switching Activity Research Articles

Design and implementation of low power multiplierless FIR filters on FPGA and ASIC

ABSTRACT This paper presents a low-power design and implementation approach for multiplierless FIR filters by reducing switching activity between filter coefficients using different optimisation algorithms. The objective function simultaneously minimises hamming distance between the consecutive filter coefficients, passband, and stopband ripples. Low-pass, high-pass, band-pass, and band-stop FIR filters of different order and word lengths are designed using improved grey-wolf optimisation. Comparison with grey-wolf optimisation, hybrid particle swarm optimisation, and grey-wolf optimisation, and whale optimisation algorithms is performed for different statistical parameters. The proposed filter is also compared with existing filter designs and shows considerable improvement in design metrics. For low-power implementation of designed FIR filters, carry-save-adder trees are utilised. FPGA and ASIC platforms are used for implementation. Basys-3 (Artix-7) FPGA board is targeted using the Vivado tool for FPGA implementation. Hardware design metrics such as slice LUTs, slice registers, slices, and dynamic power consumption are obtained. ASIC implementation is also performed using the Cadence Genus tool for a 45 nm Nan gate open cell library and total area, power, and delay are reported. The obtained results for FPGA slice utilisation and power consumption provide an average reduction of 61.39% and 74.13%, respectively. ASIC implementation provides an average 58.60% reduction in area-power product.

Low-power coding method in data transmission systems

The object of the study is the Network-on-Chip (NoC) technology, which has become a popular choice for the on-chip communication architecture of modern System-on-Chip (SoC) devices. The subject matter of the article is methods of reducing dissipated power in NoC and SoC. The goal of the work is: development of a low-power coding method that allows for the efficient transmission or storage of information. The following tasks are solved in the article: analysis of classification methods for combinatorial structures, construction a system of typical representatives and analysis of their characteristics. The research methods are based on the use of set theory, system theory and combinatorics. The following results are obtained: analyzed factors that affect the dissipated power, considered principles of constructing energy-efficient codes. It is shown that switching activity significantly affects the total power and one of the effective methods for reducing switching activity during communication between devices or on-chip communication is the use of low-power coding methods. A method of hierarchical classification of unit distance codes and algorithms for solving step-by-step problems have been developed. The method is based on the invariant approach and construction of a system of different representatives. Estimates of their number have been obtained, characteristics have been determined, and catalogs of typical representatives have been formed. Conclusions. The article analyzes factors that affect dissipated power, and considers the principles of constructing energy-efficient codes. A method of hierarchical classification of single distance codes and algorithms for solving step-by-step problems have been developed, and catalogs of typical representatives have been formed. The application of the developed method will allow developers to analyze and select codes with the best properties and, as a result, obtain better results in terms of network delays, energy costs, and other design limitations for computer systems.

Reliable single-ended ultra-low power GNRFETs-based 9T SRAM cell with improved read and write operations

This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area. Therefore, the power consumption and area of the proposed cell is enhanced by 48.9 % and 3.8 %, respectively, as compared to the 2-bitline (2-BL) 9T SRAM cell. A separate read and write port provides significant improvement in the read and write performance simultaneously. The performance of the proposed cell and other existing cells are evaluated using HSPICE-simulations. The multi-threshold technology is used to improve the performance of cells in terms of delay and power consumption. The proposed cell shows significant improvement in read stability and write-ability due to proper device sizing ratio. In nanometer regime, the cell is capable to operate at ultra low supply voltage of 300 mV due to outstanding electrical property of the GNRFETs devices.

Switching Activity Reduction of SOP Networks

Switching Activity Reduction of SOP Networks

A New Embedded Clock Gating Technique in 8- bit Synchronous Counter with Reduced Switching Activity for Clock Divider Circuit

Counters play an inevitable role in many VLSI circuits such as timers, frequency dividers, memories, and ADC/DAC. Integrating the timing discriminator, Pulse Swallow, and Correlated double sampling are various approaches used in counters for low power consumption. The main objective was to minimize the power consumption and device count. In this work, a new embedded clock gating technique is used in an 8-bit counter to reduce the switching activity. A clock gating circuit and clock buffer network pattern are used in the proposed algorithm to reduce the power consumption of synchronous counters. The proposed counter reduced the unwanted clock activity of all T FFs and noise is reduced to a greater extent thereby reducing the power and the device count. CMOS 45nm technology is used for designing the proposed counter 1.5 supply voltage. Simulated results show the improvement of the proposed approach over other conventional counters in terms of power consumption and device count.

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

A Nonlinear Function Logic Computing Architecture With Low Switching Activity

Nonlinear functions are widely involved in modern digital signal processing systems, which are usually calculated by polynomial approximation, CORDIC algorithm, or look-up tables. Due to the quite complex logic computing architectures, these methods suffer from high switching activity of logic elements, resulting in tremendous dynamic power consumption. Reducing the switching activity is believed an efficient way to save dynamic power. In this brief, we first analyzed and proved the low switching activity feature of the conventional unary number representation. Afterward, a novel multi-hot unary number representation method and the corresponding logic computing architecture with low switching activity are proposed for nonlinear function, which significantly reduces switching activity and power consumption. Moreover, the proposed nonlinear function logic computing architecture is extended to single input multiple output nonlinear function calculation, which shares the multi-hot encoder to further reduce the hardware cost. According to the post-synthesis power evaluation using PrimePower tools, the proposed architecture achieves significant switching activity and dynamic power reduction compared to conventional computing architectures.

Cluster-based test vector re-ordering for reduced power dissipation in digital circuits

Optimizing testing power is a paramount concern in modern digital circuit design, particularly as the intricacy of circuits continues to rise. This issue becomes even more pronounced with the scaling down of feature sizes due to advancements in process technology. The increase in testing power dissipation, beyond the regular operational state, raises red flags for both designers and test engineers. This paper introduces a novel cluster-based approach, shedding light on the efficient reordering of test vectors to mitigate the heightened switching activity. This technique aims to reduce the power consumption during testing, while still ensuring efficient error detection, maintaining the test period, and preserving the original order of the scan chain. Importantly, this reordering method does not introduce any additional area or test time overhead, minimizing the risks associated with these factors. The potential impact of this approach is demonstrated through concrete examples drawn from ISCAS’89 benchmark circuits. The results showcase a notable 11% reduction in switching activity, all while preserving fault coverage levels.

СODING TO REDUCE THE ENERGY OF DATA MOVEMENT

The problem of reducing power dissipation in global interconnection lines while maintaining high performance is considered in the paper. High switching activity leads to significant communication losses due to communication capacitances between long lines. New byte-addressed non-volatile memory technologies, such as phase change memory, enable systems with large persistent memory, improving reliability and potentially reducing power consumption. However, these technologies only support a limited number of write operations over the lifetime per cell, and consume most of their power when the state of a bit changes during a write. Low power coding techniques are required to reduce switching activity during device-to-device or on-chip communications. The purpose of the article is to develop a method for constructing a set of unit distance codes, analyzing their characteristics and choosing codes that satisfy the given properties. The address bus coding methods with the least switching activity are considered. To reduce dynamic energy losses in the address bus and minimize communication losses between closely spaced lines, Gray code is used, which has a number of disadvantages. Conclusions. The type of codes that have the same properties as Gray codes, i.e. unit distance codes, is determined. A method for constructing a set of unit distance codes, analyzing their characteristics, and choosing codes that satisfy the given properties has been developed. By using the entire set of codes, developers have more choices than using only Gray codes, and this leads to better results.

CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration With Better-Than-Binary Energy Efficiency

We present a 3.1 POp/s/W fully digital hardware accelerator for ternary neural networks (TNNs). CUTIE, the completely unrolled ternary inference engine, focuses on minimizing noncomputational energy and switching activity so that dynamic power spent on storing (locally or globally) intermediate results is minimized. This is achieved by: 1) a data-path architecture completely unrolled in the feature map and filter dimensions to reduce switching activity by favoring silencing over iterative computation and maximizing data reuse; 2) targeting TNNs which, in contrast to binary NNs, allow for sparse weights that reduce switching activity; and 3) introducing an optimized training method for higher sparsity of the filter weights, resulting in a further reduction of the switching activity. Compared with state-of-the-art accelerators, CUTIE achieves greater or equal accuracy while decreasing the overall core inference energy cost by a factor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.8\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$21\times $ </tex-math></inline-formula> .

A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs

Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weight-based scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC’99 and OpenRISC benchmark circuits.

Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

In this paper, a new design of low power, high performance Radix-4 MBW multiplier unit has been described. The low power performance has been achieved by dynamic voltage scaling. Based on CCGDI technique which reduces the switching activity and output capacitance, the proposed multiplier unit has been designed by utilizing three different low power methodologies i.e., reduction in output capacitance and switching activity along with biasing voltage reduction. In order to reduce the number of transistor and delay, here GDI based parallel adders are used in the Wallace tree counters. The multiplier has been implemented with constant threshold voltage PTM 45 nm devices technology and simulated in standard CAD tool simulator for 4, 8 and 16 bit operand multiplications. The proposed design consumes 238.98 µw average power and it has a propagation delay of 2.458 ns for 16 × 16 bit multiplications at speed 100 MBps which is 47% better in terms of power-delay-product than counter based GDI Wallace tree multiplier structure.

FIR Filter Design using Floating Point Column Bypassing Technique

This paper presents the design of floating point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in a FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software.

An Improved Low-Power Coding for Serial Network-On-Chip Links

In the fast nanosilicon revolution era, network-on-chip (NoC) architecture offers a significant research solution to on-chip multiprocessor-based real-time applications. As the number of cores increases, power consumption of the resources of NoC also increases. Links are the major power dissipator in NoC architecture owing to switching activity of data bits communicated through them. The performance of data communication links in NoC is strongly dependent on the factor of power dissipation. An efficient coding method is needed to reduce both coupling and self-switching activity of data bits of NoC links. In this work, an improved low-power encoding algorithm for serial links is proposed to reduce switching transition for any random data pattern making them more suited to real-time applications. The proposed encoding algorithm is coded, simulated and verified its area and power performance using Synopsys tools utilizing UMC 90 nm technology. Experimental results have shown that it provides on average 48.83% of switching activity reduction for any real-time applications.

Significance-Driven Data Truncation for Preventing Timing Failures

The continuous scaling of transistor sizes and the increased parametric variations render nanometer circuits more prone to timing failures. To protect circuits from such failures, typically designers adopt pessimistic timing margins, which are estimated under rare worst-case conditions. In this paper, we present a technique that mitigates such pessimistic margins by minimizing the number of timing failures. In particular, we propose a method that minimizes the number of long latency paths within each processor pipeline stage and constrains them in as few stages as possible. Such a method allows us not only to reduce the timing failures but also to limit the potential error-prone locations to only a few pipeline stages. To further reduce these failures, we exploit the path excitation dependence on data patterns and truncate the bitwidth of the operands in the few remaining long latency paths by setting a number of less significant bits (LSBs) to a constant value of zero. Such a truncation may incur quality loss, but this is limited since it is applied only to the LSBs of the few operands that may activate the confined error-prone long latency paths. To evaluate the efficiency of our method, we perform post-place and route dynamic timing analysis based on real operands extracted from a variety of applications. This helps to estimate the bit-error rate, while considering the data-dependent path excitation. When applied to an IEEE-754 compatible double precision floating point unit (FPU), the proposed approach reduces the timing failures by $216.25 {\times }$ on average compared to the reference FPU design under an assumed 8.1% variation-induced worst-case path delay increase in a 45-nm process. Our results show that the path shaping alone introduces a negligible 0.25% area and 5.7% power overheads with no performance cost. Finally, we demonstrate that by combining the path shaping with aggressive operand bitwidth truncation, we enable power savings up to 44.7% due to the substantially reduced switching activity at minimal quality loss.

Reduction of Power Consumption using Joint Low Power Code with Crosstalk Avoidance Code in Case of Crosstalk and Random Burst Errors

When technology is scaling down, reliability and power issues are arise in the intercommunication of System on Chip (SoC). The intercommunication links are suffers with various noise sources like crosstalk, temperature variation and voltage deflection which lead to communication link failure. To get reliable system, the strong error detection and correction codes are required. In this proposed work, Crosstalk avoidance code detects and corrects of one bit error, two bit error and some of three bit errors. The Hybrid Automatic Re-transmission Request is also used when the CAC detects the burst error of three. Apart from this, the Low Power Codes are used to get low power consumption using Bus Invert (BI) technique in proposed work. The LPC code reduces the power consumption of interconnection wires using reducing switching activity. The performance of proposed work evaluated in Xilinx 14.7 in Vertex-6 Field Programmable Gated Array (FPGA) device. The proposed work is calculated of power consumption of codec module and interconnection wire, delay of CAC and LPC code and link swing voltage. This work provides 11.7% improvement in power consumption and presents high reliability than JTEC. The energy dissipation of wires in the proposed work is decreased 23.5% than un-coded schemes.

Close-to-Functional Broadside Tests With a Safety Margin

Scan-based tests that maintain close-to-functional operation conditions are important for avoiding overtesting of delay faults while achieving the fault coverage required for avoiding test escapes. For a measurable proximity to functional operation conditions, partially functional broadside tests have a known Hamming distance between their scan-in states and reachable states. Another parameter that is important for the discussion of overtesting is the switching activity. This paper suggests a combined metric, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state. The metric is defined such that a value of 100% or lower is preferred. To demonstrate that the metric is flexible enough to allow tests to be generated, the paper describes a test generation procedure that uses the metric.

A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

This paper presents a 7-bit 15×interleaved SAR ADC that operates up to 3GS/s, using 180nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage-comparator to resolve 2bits per clock cycle, using a time-comparator block. Thus, only 5 clock cycles are needed to resolve 7bits. This results in speed improvement of about 60%, compared to conventional ADC. Also, an improved Quasi C-2C DAC structure with reduced internal node swing and reduced switching activity are utilized, which decreases the power consumption of DAC up to 65%. We employ the above techniques in designing a 7-bit SAR ADC, in which 3bits are resolved with time-comparator blocks and 4bits are resolved with a voltage-comparator. To calibrate the proposed time-comparator block, a calibration process is proposed. ADS simulation of the ADC illustrates an ENOB (Effective Number of Bits)>6.5-bit and SFDR (Spur Free Dynamic Range)=−52.8 dBc for a single SAR converter with sampling at 200MS/s. For the time-interleaved SAR ADC with 15 single SAR converters, ENOB is 6.15-bit and SFDR=−45 dBc with sampling at 3GS/s up to Nyquist frequency. This ADC consumes 150mW at 1.8V supply and achieves a Figure-of-Merit (FoM) of 700 fJ/conv-step.

An efficient architecture for carry select adder

PurposeAdders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit.Design/methodology/approachThis paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library.FindingsOptimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA.Originality/valueThe efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.