Reducing Switching Activity Research Articles

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12MHz, a 4×4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4×4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4×4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.

Adaptive Low-Power Transmission Coding for Serial Links in Network-on-Chip

The traditional Serialized Low Energy Transmission Coding (SILENT) is effective in serial links and sequential data patterns. However, it is ineffective in the multiplexed channel used on packet-switched networks because the data packets are packed and not sequential. In this paper, we propose a coding scheme for the overhead region in SILENT, and present an adapting mechanism to switch between the two coding schemes when data pattern changes, thus to minimize the power dissipation of serial links in network-on-chip. Experimental results indicate that our scheme for the overhead region is quite effective in reducing switching activity with data patterns in it. We also evaluate the efficiency of adapting coding method with two multimedia applications. Experimental results show that the method we proposed adapts to more data patterns and is more suitable for serial communication in network-on-chip.

Switching activity reduction for scan-based BIST using weighted scan input data

Switching activity reduction for scan-based BIST using weighted scan input data

Improved tracking and switching performance of an electro-pneumatic positioning system

For robotic systems that use on/off (solenoid) pneumatic actuators, a sliding mode control law for precise position control and low switching (open–close) activity of the valves is presented in this paper. Given a pneumatic actuator with two chambers and four solenoid valves, there are sixteen possible input combinations defined directly from the state of the four on/off valves present in the system; however, only seven of these discrete operating modes are considered both functional and unique. Therefore, we introduce a novel seven-mode sliding controller that minimizes the position tracking error using modes that have both the necessary and sufficient amounts of drive energy and, thus, involve reduced switching activity. An analysis of the closed-loop system stability is carried out. The performance of the proposed control design is experimentally verified on a single pneumatic actuator setup comprising of two chambers with four on/off valves.

Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus

Execution time is no longer the only target to achieve when designing programmes for today and next-generation CMOS-based digital systems. One needs to also consider reducing power dissipation. Buses contribute to the power dissipation during the execution of a given programme since instructions and/or operands have to be fetched from the memory. Reducing power dissipation in buses has been addressed in the literature. In this study, the authors address the problem of reducing power dissipation of the instruction bus by reordering the instructions in basic blocks without increasing the executing time and the code size, and while maintaining the original functionality of the programme. The authors target embedded processors having Harvard architecture. They focus on solving this problem for programmes developed at the assembly level, since at that level the machine code can be obtained by simply running an assembler, which allows an accurate computation of switching activities on the instruction bus by considering each pair of instructions. The authors formulate this problem as an integer linear programme (ILP), and they provide two heuristics. Experimental results have shown that the proposed approach can reduce switching activities. The ILP has reduced switching activities by as high as 38%. One of the two proposed heuristics has always resulted in reducing switching activities, and its relative savings are within an average of 5% from the optimum produced using the ILP.

Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing

In this work, we propose a technique to reduce switching activity while keeping leakage current under control during testing by extracting don't cares from a completely specified pattern set, and using the X bits to convert original vectors into low power vectors by a dictionary based approach. We also investigate the possibility of reducing test set length, maintaining fault coverage, by performing a tradeoff between test set volume and power. Experiments on ISCAS89 benchmark circuits validate effectiveness of our work. We could achieve an average reduction of 84.78% in dynamic power and 6.52% in leakage power for pattern set generated by the ATPG tool Atalanta. Similar savings could also be achieved on test set generated by the commercial ATPG tool Tetramax.

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression

The embedded deterministic test-based compression uses cube merging to reduce a pattern count, the amount of test data, and test time. It gradually expands a test pattern by incorporating compatible test cubes. This paper demonstrates that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions. Our novel solution produces test clusters, each comprising a parent pattern and a number of its derivatives obtained by imposing extra bits on it. In order to load scan chains with patterns that feature original test cubes, only data necessary to recreate parent patterns as well as information regarding locations and values of the corresponding conflicting bits are required. A test controller can then deliver tests by repeatedly applying the same parent pattern, every time using a different control pattern to decide whether a given scan chain receives data from the parent pattern, or another pattern is used instead to recover content of the original test cube. Compression of incompatible test cubes preserves all benefits of continuous flow decompression and offers compression ratios of order 1000× with encoding efficiency much higher than 1.0. We also demonstrate that test clusters make it possible to deliver test patterns in a flexible power-aware fashion. This framework achieves significant reductions in switching activity during scan loading as well as additional test data volume reductions due to encoding algorithms employed to compress parent and control vectors.

Reducing test-data volume and test-power simultaneously in LFSR reseeding-based compression environment

This paper presents a new test scheme based on scan block encoding in a linear feedback shift register (LFSR) reseeding-based compression environment. Meanwhile, our paper also introduces a novel algorithm of scan-block clustering. The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding. Thus, it can significantly reduce the test power and test data volume. Experimental results using Mintest test set on the larger ISCAS'89 benchmarks show that the proposed method reduces the switching activity significantly by 72%–94% and provides a best possible test compression of 74%–94% with little hardware overhead.

Low Power Bus Binding Exploiting Optimal Substructure

The earlier the stage where we perform low power design, the higher the dynamic power reduction we achieve. In this paper, we focus on reducing switching activity in high-level synthesis, especially, in the problem of functional module binding, bus binding or register binding. We propose an effective low power bus binding algorithm based on the table decomposition method, to reduce switching activity. The proposed algorithm is based on the decomposition of the original problem into sub-problems by exploiting the optimal substructure. As a result, it finds an optimal or close-to-optimal binding solution with less computation time. Experimental results show the proposed method obtains a solution 2.3-22.2% closer to optimal solution than one with a conventional heuristic method, 8.0-479.2 times faster than the optimal one (at a threshold value of 1.0E+9).

LOW POWER SHIFT AND ADD MULTIPLIER DESIGN

Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that during logic synthesis power tracks well with area. This means that a larger design will generally consume more power. The multiplier is an important kernel of digital signal processors. Because of the circuit complexity, the power consumption and area are the two important design considerations of the multiplier. In this paper a low power low area architecture for the shift and add multiplier is proposed. For getting the low power low area architecture, the modifications made to the conventional architecture consist of the reduction in switching activities of the major blocks of the multiplier, which includes the reduction in switching activity of the adder and counter. This architecture avoids the shifting of the multiplier register. The simulation result for 8 bit multipliers shows that the proposed low power architecture lowers the total power consumption by 35.25% and area by 52.72 % when compared to the conventional architecture. Also the reduction in power consumption increases with the increase in bit width.

Modified Multiply and Accumulate Unit with Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13µm Adder for Image Processing Applications

This paper explores the design approach of a low power high performance Multiply and Accumulate (MAC) unit with Hybrid Encoded Reduced Transition Activity Technique (HERTAT) equipped multiplier and low power 0.13'm adder. The developed low power MAC unit is verified for image processing systems exploiting insignificant bits in pixels values and the similarity of neighboring pixels in video streams. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. If the number of 1’s less than or equal to three the proposed encoding technique used otherwise go for Booth technique. The proposed adder cell used in the MAC block consumes less power than the other previous adder techniques. This high performance low power MAC can be used in image processing. It is observed from the device level simulation using TANNER 12.6 EDA, that the proposed scheme helps to reduce the switching activities in the MAC unit up to 19% and saves power up to 46%.

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.

An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power

Resource binding, a key step encountered in behavioral synthesis, has been studied intensively in the past. Among the published results, resource binding to reduce switching activity (SA) of the design for minimizing dynamic power has been one of the actively-pursued topics. Two types of SAs can be minimized: the intra-transition SA (occurring during the propagation of a single input vector) and the inter-transition SA (occurring between different input vectors). Previous work either ignored the inter-transition SA or provided heuristic to deal with it. When the inter-transition SA was considered, it was not clear previously whether the problem could still be solved optimally. In this paper, for the first time, we demonstrate that resource binding considering inter-transition SAs can be solved in polynomial time for designs that can be represented by data-flow graphs (DFG). This is realized by transforming the problem into finding the shortest path problem in a k-dimensional graph. We also propose an efficient heuristic that uses a network-flow algorithm followed by a legalization step using a bipartite matching algorithm. Experimental results show that a considerable amount of SA reduction can be obtained compared to the previous state-of-the-art results.

Low-Power Scan Operation in Test Compression Environment

This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a power-aware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.

A BIST TPG for Low Power Dissipation and High Fault Coverage

In This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS’89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS’89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.

Low Power Dissipation and High Fault Coverage Fault emulation of synchronous sequential circuits on FPGA

A feasibility study of accelerating fault simulation by emulation on field programmable gate arrays (FPGAs) is described. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of sequential circuits are explained. Alternatives that can be considered as trade-offs in terms of the required FPGA resources and accuracy of test quality assessment are discussed. In addition, an extension to the existing environment for re-configurable hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. This paper presents a low hardware overhead test pattern generator (TPG) for Fault Emulation that can reduce switching activity in circuits under test (CUTs) during testing and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed test pattern generation decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed method is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT- RTPG patterns are applied. The proposed approach allows simulation speed-up of 40-500 times as compared to the state-of-the-art in software-based fault simulation. On the basis of the experiments, it can be concluded that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, for example built-in self-test.

Partitioning and gating technique for low-power multiplication in video processing applications

In this paper, we propose a partitioning and gating technique for the design of a high performance and low-power multiplier for kernel-based operations such as 2D convolution in video processing applications. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, repeated values or repeated bit combinations are detected and data paths in the architecture design are disabled appropriately to eliminate unnecessary switching. Input pixels in the video stream are partitioned into halves to increase the possibility of detecting special values. It is observed that the proposed scheme helps to reduce dynamic power consumption in the 2D convolution operations up to 33%.

Design of Low Power Parallel Multiplier

Recent trends in the signal processing applications have created a need for energy efficient computation. Multiplication is a major power consuming circuit in many application areas like DSP, cryptography, and communication. This paper presents a novel architecture for the radix-2 recoded multiplier where we remove sign extended bits. The architecture is further optimized using proposed Booth Recoding Unit for low power applications. It is done by reducing switching activity on the inputs to the multiplication unit to reduce overall switching activity and hence the dynamic power consumption. We also propose an Adder-Subtractor circuit with reduced switching activity. Test Results show that the proposed design consumes 4 times less power and 15% less area than a conventional radix-2 low power recoded multiplier.

Efficient partial scan cell gating for low-power scan-based testing

Gating of the outputs of a portion of the scan cells (partial gating) has been recently proposed as a method for reducing the dynamic power dissipation during scan-based testing. We present a new systematic method for selecting, under area and performance design constraints, the most suitable for gating subset of scan cells as well as the proper gating value for each one of them, aiming at the reduction of the average switching activity during testing. We show that the proposed method outperforms the corresponding already known methods, with respect to average dynamic power dissipation reduction.

An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction

This paper presents a bus coding methodology for the instruction memory data bus switching reduction. Compared to the existing state-of-the-art multiway partial bus-invert (MPBI) coding which relies on data bit correlation, our approach is very effective in reducing the switching activity of the instruction data buses, since little bit correlation can be observed in the instruction data. Our experiments demonstrate that the proposed encoding can reduce up to 42% of switching activity, with an average of 30% reduction, while MPBI achieves just 17.6% reduction in switching activity.