Reduction In Overall Area Research Articles

Stress-free blood sampling in minipigs: A novel method for assessing 24-h cortisol profiles and drug effects on diurnal and ultradian rhythms

We developed a novel, stress-free blood sampling method for minipigs, allowing continuous cortisol monitoring over 24 h. Baseline cortisol levels exhibited both ultradian and diurnal rhythms. During nighttime, smaller ultradian rhythms overlaid a lower baseline cortisol, which increased in sleeping pigs before lights were turned on. Additionally, we developed an analytical tool based on the R package “pracma” to quantify ultradian peak and circadian components of the cortisol profiles.To validate our model, we investigated the effects of Verucerfont, a CRH receptor antagonist, and Venlafaxine, a serotonin-norepinephrine reuptake inhibitor. Verucerfont reduced cortisol levels during the first 9 h without affecting diurnal rhythm. Cortisol peak parameters decreased, with a 31% reduction in overall area under the curve (AUC) and a 38% reduction in ultradian average AUC. Ultradian peaks decreased from 7 to 4.5, with 34% lower amplitude. Venlafaxine maintained plasma concentrations within the targeted human effective range.This method enables us to enhance our understanding of cortisol regulation and provide valuable insights for the impact of investigation drugs on the diurnal and ultradian rhythms of cortisol.

An Efficient Segmented Random Access Scan Architecture with Test Compression

Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time compared to the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time. Also presented is another enhancement to incorporate a scan channel multiplex block at hierarchy segments which helps drastically decrease the area and routing overhead of the original architecture to practically implementable levels on commercial circuits. The extra Segment Data Multiplexor (SDM) blocks reduce the area overhead of other components by the multiplexing factor, and the reduction in overall area is significant based on experimental data. Test data compression and auto addressing of segments are achieved by transmitting a seed address to select segments with auto-increment or auto-decrement capability followed by either single cell selection or entire leaf cell segment selection. To further reduce the area overhead and test power, this architecture is enhanced to contain multiple channels at a cost of increased overall test application time with no increase in test data volume. Results of applying the enhancements to a large circuit with one level of intermediate segments with each of them having 256 leaf segments are presented in the paper with and without multichannel multiplexing for comparison.

Route-on-Fly Network-on-Chip Router Design with Soft-Error Tolerance

Decrease in size of IP cores, the Network-On-Chip (NOC), which is used to interconnect them, becomes more complex. NOC employ Network Interface (NI), routers and links. Chip process technology is shrinking day by day resulting in design complexities. This rises the chances of NOC becoming faulty and corrupting the packets transmitted through it. Further NOC has great influence on the complete system performance. Despite the fact that the NOC outperforms the traditional bus based interconnects, NOC faces problems with the usage of router pipeline stages. Generic pipelined router consists of Routing Computation (RC) stage, Virtual channel Allocator (VA) stage, Switch Allocator (SA) stage and CrossBar (CB) stage. These routers are more liable to hard faults and soft-errors. Hence, incorporation of an error tolerant technique to the pipeline stages is required. However, these results in area, power and delay overhead. In this paper, we proposes Route-On-Fly NOC router architecture with Soft-error tolerance (ROFNS), an optimized pipeline router with tolerance to soft errors. In addition, optimized VA stage to achieve overall reduction in area and delay penalty is also proposed. Implementation results show that there is 70%, 3% and 16% reduction in area, power and delay respectively when compared to Soft-error Tolerant NOC Router (STNR).

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems

The hardware footprint for S-box specification in lightweight block cipher as appropriate to IoT and CPS information security systems is presented in this paper. The S-box Boolean function in the lightweight block cipher is defined using the Reed-Muller structure. A Rule Based–Common Sub-structure Sharing Optimization (RB-CSSO) algorithm has been proposed towards improving the performance efficiency of Reed-Muller structure. This novel hybrid RB-CSSO optimization mechanism first transforms the direct Positive Polarity Reed Muller (PPRM) S-box representation into Mixed Polarity Reed-Muller (MPRM) S-box architecture using local rule based transformation. Secondly, the Common Sub Term (CST) and Common Sub-expression (CSE) merging/elimination are employed over the resulting MPRM structure. The combined rule-based transformation and the common sub-function sharing demonstrate an overall reduction in area, delay and power of the Reed-Muller S-box structure. Both the theoretical analysis and the experimental verification demonstrate reduction in area and delay of S-box. Post synthesis results based on ASIC standard cell based implementations have been used to analyze area, delay and power values across Process, Voltage and Temperature (PVT) corners for a wide range of operating conditions. Extensive comparisons between direct PPRM and optimized MPRM implementations have been carried out. The post layout simulations of S-box structures realized show the advantages of lower area-delay product, power-area product and power-delay product. This work thus authenticates the application of proposed structure for lightweight, resource constrained security systems. Industry standard full suite of Cadence® tools have been employed in the simulations using 65 nm TCBN65GPLUS standard cells of TSMC technology library.

An optimised twin precision multiplier for ASIC environment

In this paper, we present the performance of twin precision technique in reduced computation modified booth (RCMB) multiplier to achieve double throughput, and an algorithm is proposed. Twin precision technique is the efficient way to obtain double throughput in the multipliers. We describe how to apply twin precision technique to RCMB multipliers. Implementation of twin precision in RCMB multiplier requires lesser changes to be made in partial product array for obtaining double throughput. Multiplexers usually do the signal selection for N and N/2 bit multiplication. In RCMB multiplier, [N/2] + 1 partial product are reduced to N/2 rows. Our idea of implementing twin precision technique to RCMB results in less utilisation of multiplexers of about [N/2] + 3 which gave a way for optimization in the twin precision (TP) multiplier. Thereby, we have achieved the drastic reduction in multiplexer utilisation of about 40% to 50% (for N = 8 to 128) compared to the existing twin precision modified booth multiplier. In our proposed optimised TP modified booth multiplier this reduction in multiplexers gave a way for overall reduction in area, power and delay. Lesser utilisation of multiplexer results in the area reduction of about 5% to 18%, delay of 5% to 20% and a considerable reduction in power of 8% to 32% were noticed in the proposed TP booth multiplier for N = 8 to 128. Our proposed optimised TP multiplier is implemented in FFT complex multiplication which is taken as an application case study and achieves better performance (area, delay and power) compare to prior TP multiplier. All our evaluation are made using cadence RTL compiler using TSMC 180 nm library.

System in Package Design Case Study

In today's world, electronics need to be as small as possible. This is especially true for a wide range of electronics from UAV controllers, cellphones, to implantable medical devices. One approach to achieving small system size is the System in Package (SIP). This approach incorporates a complete system (processor, memory, etc) into one small package. On the SIP, packaged parts are replaced by dies directly mounted to the substrate via flip-chip or wire-bond technology. SIP allows the designer flexibility to create a small system with only functionality that is required. A designer can pick and choose what parts are needed for a design and is not limited to the functionality of a single signal chip. Since the first level part packaging is eliminated, the overall board size decreased leading to an overall reduction in area and weight. Not only is there a reduction in size of each packaged part, but routing area is also reduced. The line widths and spacings can be reduced along with via size. The system used in the case study is a typical system with a FPGA, flash memory, DDR3 memory, ADC, DAC, voltage monitors, power supply monitor and control. The design is a complete system capable of processing analog sensor data, recording the data in external memory and controlling analog outputs. Such a system can be used for data collection, vehicle control, data processing, etc. In terms of signal integrity, the SIP offers many advantages over a traditional PWB. Given the small nature of overall package generally means shorter routes. A shorter route has the advantage of a reduced propagation delay. Also, a shorter trace will have a lower insertion loss and improved return loss. Many parts require data busses signals to match in length. This is very important for DDR3 memory. A mismatch in trace length will cause skew between the data signals and the data strobe. On a smaller board, there is an overall improvement for matching signal traces. Power distribution is another area of improvement for the SIP. A smaller board size means the board resonances will be shifted higher in frequency, alleviating possible power rail noise issues. Overall, the power planes are less lossy. Also, decoupling capacitors will be placed closer to the active components reducing the inductive path from the active device and the capacitor. This will allow decoupling for parts switching at fast rates. Given the shorter distances between transceivers within the system, the drive strength can be reduced. Decreased drive strength will reduce the amount of power dissipated by the transceiver. This presentation details a case study for a system in package design. A comparison will be made between the system laid out on a traditional printed wiring board (PWB) and the same system laid out on a substrate (SIP). Comparisons of the area, weight, route-ability and signal integrity will be made.

Review of Compact and Broadband High Gain Micro strip Patch Antennas

Generally microstrip patch antenna (MPA) is used in modern communication devices and day-to-day communication is done through it. Study of literature of past few year shows that, the leading work on MPA is design compact size broadband microstrip antenna, but inherently MPA have narrow bandwidth so various techniques are engaged to enhance bandwidth. This review paper demonstrates some commonly engaged techniques with broader-bandwidth since last few decades to fabricate MPA. One of the advantages of microstrip patches over conventional antennas is their small size. However, there are many present day applications where even these small radiators are too large. A microstrip antenna incorporated with a single shorting pin is found to provide reduction in overall area with respect to a conventional patch. The compact circular polarized patch antennas can be achieved by slot loading on patch. In this paper the review on various techniques of compactness by Conductive vias, planar meta-material unit cell and slot loading on microstrip antenna are presented which are reported on literatures.

A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique

This paper presents a unified codec scheme for reduction of area and crosstalk in RC and RLC modeled interconnects using both bus encoding and shielding insertion technique. It is based upon bus invert method and focuses on 4 bit coupled lines. Previously used codec scheme focused independently on either RC or RLC models and they considered coupling between 5 bit coupled lines i.e. 4 bit data lines and 1 bit control line. However, our proposed codec scheme focuses on all types of couplings i.e. Type-0 to Type-4 and demonstrates an overall reduction in area as well as crosstalk considering coupling between 4 bit coupled lines and isolating the control signal using redundant shielding thus reducing the cases of coupling drastically. The proposed work has been implemented using both Semi Custom and Full Custom design approaches. The model has been described, synthesized and simulated in hardware description language VHDL along with its FPGA implementation. The power consumption has been calculated using Xpower tool of Xilinx. Same model has also been implemented using Cadence Virtuoso Analog Design Suite in 0.18um CMOS technology and the corresponding power, delay and area has been computed. The proposed scheme demonstrates an overall reduction of 76.68% in crosstalk delay and 56.33% in chip area and transistor count. 79.58% power reduction is achieved in full-custom design implementation as compared to semi-custom design implementation. DOI: http://dx.doi.org/10.11591/ijece.v3i4.3173

Glycaemic control in type 1 diabetes during real time continuous glucose monitoring compared with self monitoring of blood glucose: meta-analysis of randomised controlled trials using individual patient data

Objective To determine the clinical effectiveness of real time continuous glucose monitoring compared with self monitoring of blood glucose in type 1 diabetes.Design Meta-analysis of randomised controlled trials.Data sources Cochrane...