Voltage Ripple Reduction Research Articles

Wind Energy AC-DC Converter Voltage Ripple Reduction in Hybrid Energy System

Wind Energy AC-DC Converter Voltage Ripple Reduction in Hybrid Energy System

Control Scheme for Second Harmonic Current Elimination in Single-Star Configuration Based Cascade Multilevel Energy Storage System

Single-star configuration-based cascade multilevel energy storage system is among the most promising solution for high-voltage and large-capacity battery energy storage systems. However, such a solution has inherent second harmonic current (SHC) pulsing in each cluster, which requires a huge passive filter network to maintain the battery current ripple and the capacitor voltage ripple below a tolerable value. To address this issue, unlike the existing method using additional passive and active circuits, this letter proposes a novel SHC elimination method which is achieved by moving it to a higher order using the third harmonic voltage injection. The technique can achieve a 75% reduction of the battery current ripple and a 50% reduction of the capacitor voltage ripple, allowing the system to attain small harmonic currents or reduce the size of the passive filter. The hardware-in-the-loop results verify the effectiveness and performance of the technique under both normal and faulty grid conditions.

Voltage Ripple Suppression Methods for the Capacitor in Modular Multilevel Converter Submodules Employing a Reversed Pulse Width Modulation-Switching Channel

Modular multilevel converters (MMCs) will be widely applied in onboard integrated power systems due to their high levels of electric power output and good-quality sine waveform outputs. However, the capacitor voltage of MMCs fluctuates greatly because the charge–discharge process of the capacitor is continuous when the system is working. In order to reduce voltage ripples efficiently, a capacitor voltage ripple-suppression strategy employing a reversed PWM switching channel is proposed in this paper. For one pair of the upper and lower arm submodules, a switching channel is built. Then, the highest ripple voltage possible can be offset since the voltage fluctuation direction of the upper and the lower arm capacitors would be reversed. In addition, a clamping capacitor is added to the switching channel to further suppress the fluctuation voltage by 78%. Compared to traditional large capacitance suppression methods, only 12% capacitance is used in the proposed method. The reliability and power density of the proposed MMC both increased, and there are no additional losses compared with previous voltage ripple suppression methods. The effectiveness of the proposed voltage ripple suppression strategy is verified by simulation results.

Multi-input interleaved DC-DC converter for hybrid renewable energy applications

The increasing demand for hybrid energy systems based on renewable energy sources has enabled the new dimension for multi-input converter (MIC). Various topologies have been introduced over the last decade. However, most of these topologies have several drawbacks in terms of design complexity or efficiency. Therefore, this research aims to introduce a multi-input DC-DC converter for hybrid renewable energy applications. The proposed multi-input converter is able to hybridize different sources such as solar PV array and PEMFC. Analysis and simulation have been carried out for the double input two-phase interleaved converter in operating the boost mode. The proposed converter is designed in matlab simulink by using interleaved boost converter method to achieve a boosted and smoothened output. The proposed topology has shown a remarkable performance in terms of output voltage boosting, voltage ripple reduction as well as enhanced efficiency through interleaved boosting technique. From the simulation results, it can be observed that the proposed converter can gain high efficiency which is higher than 97%. The obtained results have been validated with previously published works and the proposed technique has been proven to yield compatible and improved outcomes.

Power losses analysis of multiphase DC-DC buck converter using OrCAD PSpice software

DC-DC buck converters have wide applications in portable electronic devices, battery chargers, and telecommunications. However, single-phase DC-DC buck converters have some drawbacks, especially in high current applications, where the increase in the size of the inductor will increase power losses, which significantly affects the overall efficiency of the converter. The multiphase configuration offers several advantages, such as reduction in output voltage ripple, input current ripple, conduction loss, and the physical size of the hardware. This paper presents an analysis of the power losses of the multiphase DC-DC buck converter with output power ranging between 50 watts to 250 watts. To verify the effectiveness of the multiphase converter, performance analysis was done using OrCAD PSpice software, where the number of phases was limited to five phases. This paper focused on power losses in the converter, namely conduction losses in diodes and MOSFETs, switching loss in MOSFETs, as well as losses in the inductor and capacitor. The relationship between the number of phases and factors of switching frequency, output, and the components’ internal resistance was also highlighted and discussed in detail.

Optimal Current Ripple PWM for Three-Level Inverter With Common Mode Voltage Reduction

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this paper proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulse width modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small and zero vectors) to reduce root mean square (RMS) value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion (THD). The effectiveness of the proposed method is validated by both simulation and experimental results.

Reduction of Output Voltage Ripple with Dc-Dc Conversion Using Ky Converter

Reduction of Output Voltage Ripple with Dc-Dc Conversion Using Ky Converter

Multiphase Digital Low-Dropout Regulators

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics (dynamic voltage scaling (DVS) speed and voltage ripple) while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/μs and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.

Improved Model Predictive Current Control for Three-Phase Three-Level Converters With Neutral-Point Voltage Ripple and Common Mode Voltage Reduction

An improved two-stage model predictive current control (MPCC) for three-phase three-level converters in the paper, which can simultaneously achieve common-mode voltage (CMV) reduction, effective dc-link capacitor voltage control, and decreased computational burden, is proposed. Compared to the other current control strategies, it has the capability of handling multiple control objectives and possesses a simple structure. Furthermore, it greatly reduces the CMV since the peak CMVs of all the candidate voltage vectors are constrained to be less than one sixth of the dc-link voltage. In addition, an optimal two-stage voltage vector selection mechanism is employed in the proposed method. It helps to significantly reduce the computational complexity. Simulation and experimental results are provided to verify the effectiveness of the proposed method.

Self-Balanced Switched-Capacitor Thirteen-Level Inverters With Reduced Capacitors Count

This letter describes two improved 13-level inverters based on switched-capacitor. Compared with their original structure, which is published recently, one less high-voltage capacitor is required in the proposed inverters and the blocking voltage of their inverting half-bridge is reduced by half. In addition, the new inverters inherit various advantages of the original structure, such as a high boost factor of 6, self-balanced capacitor voltages, and reduced voltage ripples. Circuit description, operation principle, hybrid PWM modulation, and capacitor voltage ripples are analyzed and the feasibility of the proposed inverters is finally verified by experimental results.

Analysis and design of flux cancellation power-decoupling method for electrolytic-capacitorless three-phase cascaded multilevel inverters

Cascaded multilevel inverter cells produce double-grid frequency ripples that require a large electrolytic capacitor bank for every cell, resulting in reduced system reliability and lifespan. This paper proposes a new generalized power-decoupling methodology that is applicable to any three-phase cascaded multilevel inverter topology. The proposed flux cancellation method is based on forcing a three-phase double-frequency ripple into the core of a three-phase transformer. The flux components from each phase, which are phase-shifted by 120°, cancel each other inside the core. Therefore, no power-decoupling capacitor is required in this method. A three-port bidirectional isolated converter is proposed to cancel the three-phase 120 Hz pulsating power in a single high-frequency (HF) core. High-leakage inductances and imbalances among the ports of a HF transformer are a topographical challenge. The imbalance in leakage inductances can be reduced by improving the winding schemes. However, increased leakage and imbalance among the three ports are unavoidable under high voltages because of the need for higher isolation. A universal solution involves the application of a phase shift-based controller to obtain balanced and reduced voltage ripples among the three DC links. This paper presents the dynamic analysis and controller design procedure. Results of the prototype hardware confirm the suitability of the proposed power-decoupling methods.

Capacitor voltage ripple reduction in MMC-HVDC system using flat bottom current method

Modular-multilevel converters (MMCs) are considered a useful technology in high-voltage direct current (hvdc) transmission systems. Since it offers many advantages like modular configuration with scalable output voltage. Voltage ripples on sub-module (SM) capacitors in MMC and circulating currents are two major challenges, which can affect the converter stability and performance. Conventionally, direct modulation method is used to insert or bypass SMs in MMC producing circulating current and SMs capacitor voltage oscillations. The closed loop and open loop control methods are used to overcome drawbacks in direct modulation method. However, these methods rely on the accurate measurements and estimation of SM capacitor voltages. A flat bottom current method is proposed in this paper to minimize the amplitude of ripple voltages on SM capacitors in MMC-based HVDC systems. Limited capacitor energy changes leading to reduce capacitor voltage ripples are observed by the proposed methodology using direct-modulation method without using circulating current suppression controller. The proposed method is tested on a two-terminal MMC-based HVDC system implemented by vector control approach in PSCAD/EMTDC software. Analytical results are verified by simulation results in reducing capacitor voltage ripples based on the direct modulation approach.

Operation and design analysis of an interleaved high step‐up DC–DC converter with improved harnessing of magnetic energy

SummaryIn this paper, a new interleaved DC–DC converter based on a coupled and a single input inductor is proposed. The suggested high step‐up converter utilizes various inductive and capacitive methods to transfer magnetic energy more efficiently. The output voltage is regulated with the switches' duty cycle and the coupled inductor (CI) turns ratio, which provide a wide output voltage range. Interleaving improves the converter reliability, employs both the first and third areas of CI's B‐H plane, cancels DC component of the CI, and reduces the input current ripple of the proposed converter with twice switching frequency. Utilization of two output ports for voltage stress and ripple reduction in each port, recycling the stored energy of inductances in both forward and flyback mechanisms, alleviation of switch voltage spikes, operation without circulating current, high power density, independency of switch voltage stress to the CI turns ratio, and continuous input current can be mentioned as other features. In this paper, continuous and discontinuous conduction modes' steady‐state analytics, power loss calculations, and design procedure of the proposed converter are followed with comprehensive comparisons to evaluate the capabilities. Eventually, experimental results are presented to validate theoretical calculations.

M-Type and CD-Type Carrier Based PWM Methods and Bat Algorithm-Based SHE and SHM for Compact Nine-Level Switched Capacitor Inverter

This paper presents new and efficient modulation techniques applied on the recently introduced compact nine-level switched-capacitor inverter (C9LSCI). The paper also discusses the performance of the inverter under selective harmonic elimination (SHE) and mitigation (SHM) based on the heuristic Bat-Algorithm (BA) technique. Two new modulation techniques employing CD-type carrier waves and M-type carrier waves are proposed, showing a rise in efficiency, an increase in RMS voltage, reduction in capacitor voltage ripple, and a reduction in harmonic distortion (THD). Four recently introduced modulating signals, namely the third harmonic injection, thirty-degree bus clamped PWM (THTDBCPWM), third harmonic injection sixty-degree bus clamped PWM (THSDBCPWM), one pole clamped PWM (OPCPWM). Loss balancing two-pole clamped PWM (LBTPCPWM) are applied to the inverter with the proposed carriers, and a comparative analysis is carried out on different performance parameters. The proposed carriers' efficacy in Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD), and Phase Disposition (PD) is validated. Further, Bat algorithm (BA) is applied as a heuristic approach to determine the optimum angles for the application of SHE and SHM. The efficacy of all the above techniques on the C9LSCI is verified in MATLAB/Simulink environment and further validated on an experimental setup.

An Advanced Modulation Technique Featuring Neutral Point Voltage Ripple Suppression of Three-Level Converters in High-Speed Drives

This paper introduces an advanced space vector modulation technique for three-level neutral-point-clamped (3L-NPC) converters. The studied 3L-NPC converters within aircraft electric starter generator (ESG) systems normally operate at high modulation index, low pulse ratio and full power factor range for most of the operation time. Conventional modulation techniques exhibit large neutral point voltage ripple and possible voltage imbalance under such conditions. The increase of neutral point voltage ripple implies significant increase in converter capacitor size and decrease in capacitor reliability. The modulation technique introduced in this paper achieves improved neutral point voltage balancing within each switching period through enhanced applications of small vectors and restriction on medium vectors. The advanced implementation of small vectors is achieved using a sharing factor aided by a robust incremental current prediction procedure. With the predicted machine currents, the proposed method enables the optimum application of small vectors to balance the neutral point voltages. Simulation results based on a PLECS/Simulink model and experimental results obtained from a 45kVA, 32krpm aircraft electric starter generator prototype platform validate the reduction of the neutral point voltage ripple.

A Fundamental Study on Voltage Ripple Reduction of Cell Capacitors of MMC Applied to DC Power Transmission

A Fundamental Study on Voltage Ripple Reduction of Cell Capacitors of MMC Applied to DC Power Transmission

A Novel Battery Integration Method of Modular Multilevel Converter With Battery Energy Storage System for Capacitor Voltage Ripple Reduction

Modular multilevel converter with integrated battery energy storage system has been verified as a better choice for large-scale battery energy storage system. However, battery power and its unbalanced distribution in submodules lead to significant increase of capacitor voltage ripple. Larger submodule capacitance is required to maintain the ripple within reasonable limits, increasing the cost and volume of the system. To address the problem, this article proposes a novel battery integration method. Each battery pack is connected with two submodules that belong to upper and lower arm, respectively, through an isolated three-port dc-dc converter. The proposed method can ensure the power balance between upper and lower arm to eliminate fundamental circulating current and reduce capacitor voltage ripple. Three-port converters provide power channels for the fundamental power fluctuation of arms; thus, capacitor voltage ripple is further reduced. Then, the small-signal model of the proposed structure is built, and the control strategy is designed to realize both capacitor voltage ripple reduction and battery power control. Finally, a downscaled prototype is built and detailed experiment results verify the effectiveness of the proposed battery integration method and control strategy.

Reliability and Performance Improvement of PUC Converter Using a New Single-Carrier Sensor-Less PWM Method With Pseudo Reference Functions

A new single-carrier sensor-less pulsewidth modulation (PWM) method using suggested pseudo reference functions is proposed for packed U-cell (PUC) converter to improve performance and reliability of the PUC converter. It is composed of one PWM carrier signal and two suggested pseudo reference functions. By employing the proposed modulation method, the PUC dc capacitor voltage ripple is substantially decreased, and faster sensor-less capacitor voltage balancing is obtained. Moreover, the power losses are evenly distributed among all power switches. Consequently, notable reduction of the PUC dc capacitor voltage ripple and even distribution of the power loss among switches enhance the PUC converter's reliability and lifetime. In addition, odd multiples of the switching harmonic clusters are eliminated from the output voltage; thus, the values of output passive filter components are halved. Hence, applying the proposed single-carrier sensor-less PWM method remarkably improves the performance, power density, reliability, and lifetime of the PUC converter and notably simplifies implementation of the switching pattern. Provided experimental results and comparisons as well as reliability analysis verify the viability and effectiveness of the proposed PWM method.

수소연료전지 하이브리드 철도차량용 병렬입력-직렬출력 구조 다중 공진형 LLC 컨버터의 모듈 출력 불평형 및 전압전류 리플 저감을 위한 제어 기법 연구

수소연료전지의 출력을 고압의 철도추진시스템의 입력으로 사용하기 위해서는 안정된 고전압을 생성하기 위해 승압형 컨버터가 필요하다. 또한 승압형 컨버터는 차량 내부에 탑재되기에 적은 부피와 손실이 요구되며, 고효율 고밀도 특성을 가진 LLC 공진형 컨버터를 승압형 컨버터로 사용하기 위한 연구가 활발히 진행중이다. 특히 이들 연구 중 병렬 입력-직렬 출력 구조의 다중 LLC 공진형 컨버터는 다중 컨버터 모듈로 Q인자를 낮춰 넓은 입출력 범위와 효율의 최적화가 가능하며, 직렬 출력 구조로 소자의 내압을 낮출 수가 있어 매우 각광받고 있다. 하지만 공진탱크의 소자 편차로 인해 최대 15% 모듈 출력 전압 편차가 발생되고 이는 개별 컨버터 모듈의 출력 불평형을 초래하며, 직렬 출력 구조로 인해 출력 전압 리플이 누적되어 큰 전압 리플을 발생시킨다. 본 논문에서는 LLC 공진형 컨버터에 주파수/시비율 복합제어를 통해 개별 LLC 컨버터 모듈의 출력 전압과 출력 불평형을 저감하고, 모듈들의 인터리빙 제어를 통해 직렬 출력의 출력 전압 리플을 저감하는 제어 기법을 제안한다. 제안된 제어를 통해 모듈 간 출력 불평형을 최소화 하여 컨버터 모듈의 최적화 설계가 가능할 뿐만 아니라, 모듈의 수명을 일정하게 관리하여 유지보수가 용이하고, 또한 직렬 출력의 출력 전압 리플을 최소화 하여 추진 시스템에 안정된 전력 공급이 가능하다.

Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method During Inductors Mismatch Condition

Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this article, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulsewidth modulation technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset.