Reduced Switch Count Research Articles

A Reduced Switch Count Three-Phase AC/AC Converter With Six Power Switches: Modeling, Analysis, and Control

Reducing the number of semiconductor switches in power electronics converters has been a continuing effort in recent years as a measure to enhance the system reliability and to decrease its size, weight, and component cost. For these reasons, a new reduced switch count three-phase ac/ac converter is being proposed. Being realized by only six active switches and antiparallel diodes, the proposed converter topology employs the minimum number of semiconductor devices amongst the converters of its kind. It also features unity power factor, regenerative operation, pulsewidth-modulated output voltage, and sinusoidal input current. The reduced number of switches results in a simplified associated gate drive circuit as well as cooling system which, in turn, may reduce the overall manufacturing cost and increase the reliability, especially in low-voltage and low-power applications. The modulation scheme of the new converter is developed, and a control algorithm is proposed for the converter’s rectifier side. Moreover, an analysis is performed on the dc-link capacitor sizing for the purposes of reducing the dc-link voltage ripple, and balancing the input current and lowering its total harmonic distortion. The simulation and experimental results corroborate the transient and steady-state performance of the proposed converter topology.

Active-Phase Converter for Operation of Three-Phase Induction Motors on Single-Phase Grid

The operation of a three-phase induction machine on single-phase supply has been an approach used for electromechanical energy conversion in rural communities with limited or no access to the three-phase grid. Such single-phase to three-phase conversion can be achieved by passive and active means. In passive methods, fixed capacitors are used for starting and running the motor. Single-phase to three-phase conversion with reduced switch count is desirable, as this leads to a lower cost. However, it is a challenge to start an induction motor using such a power converter and to maintain balanced three-phase voltage under all loading conditions. It is shown in this work that balanced excitation cannot be achieved under all conditions with variable capacitor emulation method. An active phase-converter configuration and its control that ensures balanced three-phase power supply at the motor terminals under all operating conditions is proposed. Also, this approach has the ability to soft-start the motor. It is shown that this can be done without drawing excessive currents from the power converter or from the single-phase grid. A design methodology is presented for the selection of the autotransformer taps to limit startup transient currents to the desired level, based on the analytical results. Simulation and experimental results are presented that validate the proposed topology and control.

Reduced Active Switch Front-End Multipulse Rectifier With Medium-Frequency Transformer Isolation

This paper presents a reduced switch count multipulse rectifier with medium-frequency (MF) transformer isolation. The proposed topology consists of a three-phase push–pull based ac to dc rectifier with a MF ac link employing two active switches. A three-phase, five-limb, multiwinding MF transformer is employed for isolation. The secondary side of the transformer is connected in a zig-zag configuration and is fed to two six-pulse diode rectifiers, achieving 12-pulse rectifier operation. The primary advantage of the proposed system is reduction in size/weight/volume compared to the conventional 60 Hz magnetic transformer isolation rectifier system. Operating the transformer at 600 Hz is shown to result in three times reduction in size. Furthermore, the proposed system employs only two active semiconductor switching devices operating under a simple pulse width modulation scheme. Also, the zig-zag transformer connection helps to balance leakage inductance on the secondary side. Detailed analysis, simulation, and experimental results on a 208Vl-l, 3.15 kW laboratory prototype are presented to validate the performance of the proposed approach.

A Single-Phase Buck Matrix Converter With High-Frequency Transformer Isolation and Reduced Switch Count

In this paper, a new type of matrix converter (MC) also called a single-phase high-frequency transformer isolated (HFTI) buck MC is proposed. The proposed converter can provide step-down operation of the input voltage with various types of output voltages such as in-phase and out-of-phase output voltages, rectified (or positive) output voltage, and output voltage with step-changed frequency. By incorporating HFT isolation, the proposed MC saves an extra bulky line frequency transformer, which is required for the conventional MCs to provide electrical isolation and safety, when used in application such as dynamic voltage restorers, etc. Two different circuit variations of the proposed HFTI MC are presented with and without continuous output currents, with the latter having less passive components. The safe-commutation strategy is also employed for the proposed HFTI MC to provide current path for the inductor during dead-time, which avoids switch voltage spikes without adding any snubber circuits. The operation principle and circuit analysis of the proposed MC are presented, and switching strategies are also developed to obtain various output voltages. Moreover, a prototype of the proposed MC is fabricated, and experiments are performed to produce in-phase/out-of-phase and rectified output voltages, and output voltage with step-changed frequency.

Fault Ride Through and Grid Support Topology for the VSC-HVDC Connected Offshore Wind Farms

Voltage source converter (VSC) based high voltage direct current (HVdc) transmission draws more attention in recent years for the grid connection of large-scale offshore wind farms (WF). This paper proposes nine switch converter (NSC) based configuration and control strategy for the VSC-HVdc connected offshore WFs to enhance the fault ride through operation of the system. The configuration allows having both shunt and series interfaces to the onshore grid, which allows the isolation of the faulty part of the network, continuous power delivery to the healthy portion, and significant reduction of the fault current. Reduced switch count NSC is utilized at the onshore station to provide simultaneous shunt and series compensation to the electric grid. The proposed control strategy ensures full power evacuation and the dc-link voltage regulation during network disturbances. The comparative analysis between the proposed and conventional VSC-HVdc systems carried out in MATLAB/ Simulink environment revealed the former's enhanced transient performance.

Improved pulse‐width modulation scheme for T‐type multilevel inverter

In recent times, reduced switch count multilevel inverter (RSC-MLI) has become an emerging area of research in power electronic converters. To control these RSC-MLI topologies, various novel modulation schemes are reported. Multi-reference is one of such modulation scheme reported for various RSC topologies, such as T-type. However, the performance of this conventional scheme results in high total harmonic distortion (THD) in line voltages, when compared with the conventional level shifted pulse-width modulation scheme. This observation is clearly presented in this study and the reason for its degraded THD performance has been deeply discussed. To alleviate this problem, a modified multi-reference dual-carrier modulation technique with multiple references and two carriers is proposed. To implement this proposed modulation technique, an alternate carrier and modulation signals arrangement with multiple carriers and single reference is also presented. Finally, a comparative THD performance of the proposed and conventional modulation schemes is carried out on a five-level T-type MLI and obtained simulation results are validated experimentally.

A Highly Efficient and Reliable Inverter Configuration Based Cascaded Multilevel Inverter for PV Systems

This paper presents an improved cascaded multilevel inverter (CMLI) based on a highly efficient and reliable configuration for the minimization of the leakage current. Apart from a reduced switch count, the proposed scheme has additional features of low switching and conduction losses. The proposed topology with the given pulse width modulation (PWM) technique reduces the high-frequency voltage transitions in the terminal and common-mode voltages. Avoiding high-frequency voltage transitions achieves the minimization of the leakage current and reduction in the size of electromagnetic interference filters. Furthermore, the extension of the proposed CMLI along with the PWM technique for 2 m + 1 levels is also presented, where m represents the number of photovoltaic (PV) sources. The proposed PWM technique requires only a single carrier wave for all 2 m + 1 levels of operation. The total harmonic distortion of the grid current for the proposed CMLI meets the requirements of IEEE 1547 standard. A comparison of the proposed CMLI with the existing PV multilevel inverter topologies is also presented in the paper. Complete details of the analysis of PV terminal and common-mode voltages of the proposed CMLI using switching function concept, simulations, and experimental results are presented in the paper.

Hybrid Modular Multilevel Converter Based Single-Phase Grid Connected Photovoltaic System

This paper presents a new single-phase Hybrid Modular Multilevel Converter (HMMC) topology with reduced number of sub-modules and its application in grid integration of Photovoltaic (PV) systems. This HMMC has reduced switch counts as compared to other existing multilevel topologies and so has potential advantages like reduction in converter losses and size, high efficiency, fewer circuit complexities, and the cost. The modified ripple correlation control (RCC) based maximum power point tracking (MPPT) is used to extract maximum power from the PV systems. A control strategy has been proposed for the control of the injected active and reactive power to the grid. The overall system has been simulated using MATLAB/Simulink platform, and the results are presented to support the theoretical concepts about HMMC with the control scheme proposed for the specific application.

Reduced switch count pulse width modulated multilevel inverter

The study develops a new topology for a single phase cascaded H-bridge multilevel inverter (CHBMLI) with a focus to reduce the number of power switching devices in the path for the flow of current. The philosophy combines an array of series connected voltage sources on either side of an H-bridge inverter to derive the new configuration for the MLI. It allows a multicarrier pulse width modulation approach to the process of generating the pulses for synthesising the PWM output voltage. The use of a smaller number of switches to reach the output voltage show cases the ability of the modular architecture to expand the scope of the CHBMLI. The architecture of a field programmable gate array fosters to realise its implementation and validate the simulated results over a range of modulation indices. The performance draws a new directive in the choice of a particular topology for the MLI to suit applications in the real world.

Novel Family of Single-Phase Modified Impedance-Source Buck-Boost Multilevel Inverters With Reduced Switch Count

This paper describes novel single-phase solutions with increased inverter voltage levels derived by means of a nonstandard inverter configuration and impedance source networks. Operation principles based on special modulation techniques are presented. Detailed component design guidelines along with simulation and experimental verification are also provided. Possible application fields are discussed, as well as advantages and disadvantages. Finally, future studies are addressed for the new solutions.

Reduced Switch Count Topology of Current Flow Control Apparatus for MTDC Grids

The increasing demand for high voltage DC grids resulting from the continuous installation of offshore wind farms in the North Sea has led to the concept of multi-terminal direct current (MTDC) grids, which face some challenges. Power (current) flow control is a challenge that must be addressed to realize a reliable operation of MTDC grids. This paper presents a reduced switch count topology of a current flow controller (CFC) for power flow and current limiting applications in MTDC grids. A simple control system based on hysteresis band current control is proposed for the CFC. The theory of operation and control of the CFC are demonstrated. The key features of the proposed controller, including cable current balancing, cable current limiting, and current nulling, are illustrated. An MTDC grid is simulated using MATLAB/SIMULINK software to evaluate the steady state and dynamic performance of the proposed CFC topology. Furthermore, a low power prototype is built for a CFC to experimentally validate its performance using rapid control prototyping. Simulation and experimental studies indicate the fast dynamic response and precise results of the proposed topology. Furthermore, the proposed controller offers a real solution for power flow challenges in MTDC grids.

Predictive control of power flow between two islanded microgrids using nine-switch converter

Nine-switch converter has been recently known for its higher compactness with reduced switch count as compared to the back-to-back converter. The readily available dc-link capacitor made it an appropriate alternative for ac/dc/ac conversion in microgrids. Regardless of the complicated Pulse Width Modulation control scheme, this paper proposes a novel predictive power control for the nine-switch converter which is simple and allows concurrent control of real and reactive power flow between two islanded microgrids. The proposed control scheme adopts the virtual flux vectors and a newly defined reactive power to improve the power quality under the existence of grid voltage disturbances, i.e., voltage unbalance and voltage distortion. Simulation results of the proposed predictive power control guarantee decoupled active and reactive power controls, fast response, accurate power and dc-link voltage tracking, and sinusoidal current waveforms with low harmonic distortions under the various grid conditions.

A Preprocessed PWM Scheme for Three-Limb Core Coupled Inductor Inverters

A discontinuous pulse-width modulation (PWM) scheme is presented for a six-switch three-limb coupled inductor inverter. Three-level PWM phase output voltages are produced with a reduced switch count and reduced dv/dt stresses on loads and output filters. The PWM scheme described lowers the coupled inductor and semiconductor losses by lowering the inductor winding high-frequency current ripple using two techniques: 1) winding excitation flipping within each carrier cycle; and 2) the inductor magnetic flux is kept within the three-limb core, neglecting natural leakage, by avoiding switching states that produce common-mode voltage excitation of the three-limb inductor. To make best use of the nonstandard switching patterns produced, reference signals are preprocessed before being delivered to the PWM modules using only one carrier signal: representing an approach well suited for implementation in a low-cost digital signal processor. The digital output signals of each PWM module represent the desired switching states of each switch in the inverter. This approach contrasts with previous published work, where postprocessing of the PWM module output signals is necessary using digital logic circuitry, such as a field-programmable gate array. Experimental results, with inductor loss and inverter efficiency comparisons for different operating conditions, confirm that the three-phase six-switch inverter PWM patterns lower the high-frequency current ripple in the inductor windings and, hence, significantly lower the inverter losses and increase the power conversion efficiency.

Performance Evaluation of 3Φ Asymmetrical MLI with Reduced Switch Count

The multi level inverter system is habitually exploited in AC drives, when both reduced harmonic contents and high power are required. In this paper, a new topology for three phase asymmetrical multilevel inverter employing reduced number of switches is introduced. With less number of switches, the cost, space and weight of the circuit are automatically reduced. This paper discusses the new topology, the switching strategies and the operational principles of the chosen inverter. Simulation is carried out using MATLAB-SIMULINK. Various conventional PWM techniques that are appropriate to the chosen circuit such as PDPWM, PODPWM, APODPWM, VFPWM and COPWM are employed in this work. COPWM technique affords the less THD value and also affords a higher fundamental RMS output voltage.

Microgrid Power Quality Improvement by using Dual Output Four-Leg Inverter

In this paper, a new system is proposed for connecting a microsource to a weak utility. The proposed system simultaneously conditions the quality of the power supplied to the microgrid loads. This system employs a recently introduced reduced switch count dual-output inverter in a so-called equal frequency mode which offers its best operation features such as maximum dc bus voltage utilization and minimum device ratings. Compared to the counterpart system, the proposed configuration enjoys an integrated structure and uses less number of semiconductor switches. Moreover, it retains the desirable features of the conventional system such as ability to compensate unbalanced/sagged utility and to supply three-phase unbalanced loads with balanced and ceaseless voltage. The proposed system is introduced and its carrier-based modulation scheme is elaborated. Subsequently, a detailed study on the maximum achievable modulation index under different working conditions is carried out. The report concludes with a discussion on control of the system and its controller design. The validity of operation of the proposed system is verified through simulation. Keywords —Distributed generation (DG), dual-output four leg inverter, microgrid.

Generalized Carrier-Based PWM Method for a 12-Switch Converter

Abstract This paper proposes a generalized carrier-based pulse-width modulation (CBPWM) method for a 12-switch converter feeding three independent loads. The converter topology is part of the (3N + 3)-switch converter family where N is the number of outputs (N = 3 for this special case). Its more famous sibling is the 9-switch converter which is gaining considerable interest from researchers because of its reduced-switch count architecture. The structure and limitations of the converter are elaborated; its modulation method applicable to both equal and different frequency (and/or amplitude) operations is formulated. The generalized neutral voltages for the converter is derived for the first time and used as the offset voltages required by this type of topology to decouple its three outputs. The proposed algorithm is validated by both theoretical simulations and experimental results.

Single-Phase to Three-Phase Converters With Two Parallel Single-Phase Rectifiers and Reduced Switch Count

This paper presents two single-phase to three-phase conversion systems for a three-phase load application. The load is connected to a single-phase grid through an ac–dc–ac single-phase to three-phase converter. The single-phase rectifier is composed of two parallel single-phase half-bridge rectifiers. The first proposed topology is composed of a full-bridge three-phase inverter, i.e., three-leg inverter, while the other topology is composed of a two-leg inverter. Suitable modeling, including the circulation current, and control strategy are presented. A pulsewidth modulation (PWM) technique using a single or double carriers PWM implementation is presented. Proposed topologies permit to improve the harmonic distortion. In addition, the P5L converter can reduce the converter power losses. Finally, simulation and experimental results are presented for validation purposes.

State Space Modeling and Implementation of a New Transformer Based Multilevel Inverter Topology with Reduced Switch Count

This paper presents a new transformer based multilevel inverter, with a novel pulse width modulation scheme to achieve seven-level inverter output voltage. The proposed inverter switching pattern consists of three fundamental frequency sinusoidal reference signals with an offset value, and one high frequency triangular carrier signal. This switching scheme has been implemented using an 8-bit Xilinx SPARTAN-3E field programmable gate array based controller. In addition, the state space model of the proposed inverter is developed. The significant features of the proposed topology are: reduction of the power switch count and the gate drive power supply unit, the provision of a galvanic isolation between load and sources by a centre tap transformer. An exhaustive comparison has been made of the existing multilevel inverter topologies and the proposed topology. The performances of the proposed topology with resistive, resistive-inductive loads are simulated in a MATLAB environment and validated experimentally on a laboratory prototype.

Analysis of Reduced Switch Topology Multilevel Inverter with Different Pulse Width Modulation Technique and Its Application with DSTATCOM

Multilevel inverter has played a vital role in medium and high power applications in the recent years. In this paper, Reduced Switch Count Multi Level Inverter structure (RSCMLI) topology is presented with different pulse width modulation techniques. The harmonic level analysis is carried out for the reduced switch count multilevel inverter with the different PWM technique such as with Alternate Phase Opposition Disposition (APOD) method, In Phase Disposition (IPD) method and multi reference pulse width modulation method for five level, seven level , nine level and eleven level inverter. The simulation results are compared with the cascaded H Bridge Multi Level Inverter (CHBMLI). The nine level RSCMLI inverter with APOD method is used for the Distribution Static Synchronous Compensator (DSTATCOM) application in the nonlinear load connected system for power factor improvement. The result shows that the harmonic level and the number of switches required for RSCMLI is reduced compared to CHBMLI. RSCMLI employed in DSTATCOM improves the power factor and harmonic level of the system when it is connected to the nonlinear load.

Investigation of single phase reduced switch count asymmetric multilevel inverter using advanced pulse width modulation technique

In this paper, a new topology for Multilevel Inverter (MLI) with reduced switch count is proposed with an asymmetric dc source configuration. This configuration is used to double the output voltage level in multilevel inverter based on switched dc sources, by adding two switches with dc sources. The increased number of levels in the output voltage reduces the filtering requirements. The working principle of the proposed asymmetric inverter is presented through the single phase fifteen level inverter. The harmonic contents of different modulation indices are examined. The performance analysis of the inverter is compared with trapezoidal and Sinusoidal Pulse Width Modulation (SPWM) in terms of Total Harmonic Distortion (THD), fundamental rms voltage (V rms ) and Crest Factor (CF). The simulation results for the same are evaluated using MATLAB/SIMULINK