Reduced Switch Count Research Articles

Multilevel Inverter: A Survey on Classical and Advanced Topologies, Control Schemes, Applications to Power System and Future Prospects

In recent years, multilevel inverters (MLIs) have emerged to be the most empowered power transformation technology for numerous operations such as renewable energy resources (RERs), flexible AC transmission systems (FACTS), electric motor drives, etc. MLI has gained popularity in medium- to high-power operations because of numerous merits such as minimum harmonic contents, less dissipation of power from power electronic switches, and less electromagnetic interference (EMI) at the receiving end. The MLI possesses many essential advantages in comparison to a conventional two-level inverter, such as voltage profile enhancement, increased efficiency of the overall system, the capability of high-quality output generation with the reduced switching frequency, decreased total harmonic distortions (THD) without reducing the power of the inverter and use of very low ratings of the device. Although classical MLIs find their use in various vital key areas, newer MLI configurations have an expanding concern to the limited count of power electronic devices, gate drivers, and isolated DC sources. In this review article, an attempt has been made to focus on various aspects of MLIs such as different configurations, modulation techniques, the concept of new reduced switch count MLI topologies, applications regarding interface with renewable energy, motor drives, and FACTS controller. Further, deep insights for future prospective towards hassle-free addition of MLI technology towards more enhanced application for various fields of the power system have also been discussed. This article is believed to be extremely helpful for academics, researchers, and industrialists working in the direction of MLI technology.

Seven-Level Symmetrical Series/Parallel Multilevel Inverter with PWM Technique Using Digital Logic

This paper attempts to come up with a proposed configuration of Multilevel inverters with a lesser number of switches that are smaller in size, lesser in cost and with a higher efficiency. Designing an inverter topology with a lesser number of switches and proper control technique is the major challenge. cascaded H-Bridge (CHB) topology are more popular among the existing configurations of multilevel inverters (MLI). Even though it can produce more levels, it needs to accommodate a huge number of switches for higher levels. The focus of this paper is to reduce the number of components for the same voltage level of cascaded H- Bridge configuration. In addition to that, generating the gating pulses for the switches is difficult when there is an asymmetry in the switches. A new symmetrical series/parallel configuration is proposed with reduced switch count and the pulse width modulation (PWM) technique is implemented with digital logic to generate the required gating pulses for the switches. The total harmonic distortion (THDI) of the output current is reduced with this PWM technique. The simulation has been carried out in MATLAB/Simulink software for both R (resistive) and R-L (resistive -inductive) loads.

Active voltage balancing strategy of asymmetric stacked multilevel inverter

Multilevel inverters (MLI) play an important role in AC applications and are undergoing continuous development in topology and control. In higher levels inverters, conventional MLIs have high components count which calls for modification of these topologies to obtain the same number of levels with fewer components to reduce cost and size. Balancing of the capacitors voltages is crucial for the operation of the MLI and it becomes more challenging in higher levels. This paper presents an active voltage balancing strategy for a reduced switch count five-leve topology which is the asymmetric stacked multilevel inverter (ASMLI). The ASMLI uses fewer components than the conventional MLIs when used in their five-levelconfiguration. The proposed active voltage balancing strategy uses simple measurements and logic to assure a balanced capacitors voltages during steady state and transients. The performance was examined and compared based on two modulation techniques with LCL filter and RL load using MATLAB/Simulink. The results show that the active voltage balancing strategy can trace all capacitors voltages to the reference value simultaneously with less than 1% voltage error, fast dynamic response, and an acceptable total harmonic distortion (THD) which allows the proposed setup to be an available option for medium voltage applications.<br /><div> </div>

A Reduced Switch Count Seven Level Symmetrical Inverter with Low Distortion

Various types of new structures in multilevel inverters are evolving day by day. One among those is the reduced switch count type multilevel inverters. This inverter consists of low number of switches, gate driver components, and other switches like auxiliary switches. Depending on the value of the voltage sources we have symmetrical and asymmetrical multilevel inverters. In this paper, the seven level symmetrical inverter design is shown for seven levels in its output. The output voltage waveform is plotted and its FFT is performed and the THD values are shown. The inverter is simulated in SIMULINK software. Index Terms: Seven level MLI, inverter, and Modular Inverter.

Retraction: Reduced Switch Count Multilevel Inverter with Fault Diagnosis Operation (J. Phys.: Conf. Ser. 1916 012100)

This article (and all articles in the proceedings volume relating to the same conference) has been retracted by IOP Publishing following an extensive investigation in line with the COPE guidelines. This investigation has uncovered evidence of systematic manipulation of the publication process and considerable citation manipulation.IOP Publishing respectfully requests that readers consider all work within this volume potentially unreliable, as the volume has not been through a credible peer review process.IOP Publishing regrets that our usual quality checks did not identify these issues before publication, and have since put additional measures in place to try to prevent these issues from reoccurring. IOP Publishing wishes to credit anonymous whistleblowers and the Problematic Paper Screener [1] for bringing some of the above issues to our attention, prompting us to investigate further.[1] Cabanac G, Labbé C and Magazinov A 2021 arXiv:2107.06751v1 Retraction published: 23 February 2022

Reduced Switch Count Multilevel Inverter with Fault Diagnosis Operation

This paper proposes a reduced switch count multilevel inverter with fault diagnosis operation to overcome the problem of a higher number of switches in a multilevel inverter and fault detection in a multilevel inverter. A multilevel inverter is a power electronic device with low switching losses and low total harmonic distortion that is used in high voltage and high power applications (THD). In a standard inverter, it’s often used to minimise the size and number of passive filters. The H-bridge topology is needed for the proposed model of reduced switch count multilevel inverter (RSC – MLI). It is used to achieve higher power ratings as well as to promote the use of renewable energy sources. It reduces switching errors and the number of power electronic switches, cost and lower order harmonics. As the number of levels and steps in the waveform increase, the harmonics in the output voltage waveform decrease, resulting in an ideal waveform that looks like a sinusoidal waveform, which reduces the harmonics at the output. Switching losses and power losses can be minimised by using a limited number of switches.

Low-Frequency Selection Switch Based Cell-to-Cell Battery Voltage Equalizer With Reduced Switch Count

A selection switch based cell-to-cell voltage equalizer requires only one dual-port dc-dc converter shared by all the cells. A cell-to-cell voltage equalizer is proposed that utilizes a capacitively level-shifted Cuk converter and low-frequency cell selection switches. The absence of isolation transformer and diodes in the equalizer leads to high efficiency, and the use of low-frequency selection switches significantly reduces the cost of the drive circuits. A low-frequency cell selection network is proposed using bipolar voltage buses, where the switch count is almost half, compared to the existing low-frequency cell-to-cell equalizers for the case of a large number of cells. A novel approach for cell voltage recovery compensation is proposed, which reduces the number of operations of the selection switches and the equalization time. The proposed equalizer is implemented with relays and verified with an eight-cell Li-ion stack. The developed prototype shows the efficiency of over 90% and good voltage balancing performance during charging, discharging, and varying load conditions. Experimental results also show about one order of magnitude reduction in the number of relay switchings and a significant reduction in equalization time using the proposed voltage compensation.

A Reduced Switch Count and THD Analysis in Cascaded H Bridge Multi-level inverter Topology

Designing of a multilevel inverter is required for power conversion with good efficiency, less switching loss, less THD values related to voltage and current . In a multi-level inverter, the desired output value depends on the harmonic values so as to increase the levels in output. This paper presents a 9-level cascaded H bridge inverter and a reduced number of switching devices.The developed H bridge inverter is analyzed in terms of THD values at different loads. The developed H bridge inverter is compared with PD,POD,APOD techniques in terms of THD values. Based on simulation results it has been observed that the developed H bridge inverter system performs well in terms of voltage and current THD values and achieve good efficiency due to less loss.

Space vector pulse width amplitude modulation strategy for three-level direct matrix converter

The total harmonic distortion and switching stress of a three-level direct matrix converter (TLDMC) is greatly reduced in comparison with those of a conventional matrix converter (MC). Meanwhile, the TLDMC leads to major advantages in comparison with existing multi-level AC–DC–AC converter topologies in terms of reduced switch counts and lowered switching power loss. In this paper, a space vector pulse width amplitude modulation (SVPWAM) strategy for the TLDMC is proposed, which can reduce the number of switching actions and improve the voltage utilization by eliminating the zero vector of each sector. An indirect modulation model of a TLDMC is discussed according to the topology of TLDMC in this paper. For the space vector modulation of the TLDMC, the space vector pulse width modulation (SVPWM) with a zero-vector of the fictitious rectifier stage is improved to form the SVPWAM. In addition, the virtual space vector pulse width modulation (VSVPWM) strategy is used for the fictitious inverter stage. Finally, simulation and experimental results verify the correctness of the proposed method.

A new family of boost active neutral point clamped inverter topology with reduced switch count

A new family of inverter topology for active neutral point clamped (ANPC) is proposed. The traditional ANPC gives the output voltage of half the input voltage which necessitates the use of higher input dc-link voltage. To fix this problem, a floating capacitor is used to increase the voltage of the output, which decreases the dc-link requirement. Moreover, no sensors are needed to stabilize the floating condenser for the proposed topology, which minimizes inverter complexities. The neutral point is connected directly to the load terminals, which decreases the leakage current and makes it suitable for solar PV integration. Two modes of operation of the proposed topology have been discussed while considering the voltage of the floating capacitor used in the topology. Furthermore, two extensions of the proposed topology with generalized structure have also been provided in the paper. A detailed comparison with similar topologies has been provided. The level-shifted pulse width modulation technique has been used for the control of the proposed active neutral point clamped topology. In order to illustrate the idea of the proposed active neutral point clamped inverter, the theory of operation and analysis is accompanied by simulation, and experimental waveforms obtained from a laboratory prototype are provided.

Experimental validation of nine‐level switched‐capacitor inverter topology with high voltage gain

SummaryThis paper proposes a new switched‐capacitor nine‐level (9L) inverter with reduced switch count. In the proposed topology, floating capacitor (FC) is employed as a voltage booster, and it does not need any additional sensors to maintain the voltage across the FC. Due to additional FC, the number of dc sources and voltage stress on switches is reduced. Moreover, the proposed topology can be cascaded to achieve more voltage levels. Various parameters are considered in the comparison of the proposed topology with other recent switched‐capacitor topologies. Simulation and experimental results demonstrate the performance with different load and modulation index variations.

A Developed H-Bridge Cascaded Multilevel Inverter with Reduced Switch Count

Multilevel Inverter integrates several Direct Current (DC) sources to produce a single-phase Alternating Current (AC) waveform that can be used to meet the domestic and commercial power demand. This article introduces a novel Multi Source Cascaded Multilevel Inverter with a reduced number of switches for the efficient use of DC voltage sources. The conversion efficiency can be increased by the presented topology which is simple in design to overcome the significant switching losses in the power electronics devices. Optimal Firing Angle and Phase Opposition Disposition Pulse width Modulation Techniques were used to reduce the harmonics at the desired output of the inverter and also to improve the power quality of the presented topology. This article also proposes two Asymmetric Multilevel Inverter Topologies. A comparison has been made, on the number of switches required and the efficiency of the inverters to differentiate the presented Topologies from other topologies of the multilevel inverter. Finally, the performance characteristics of the presented topologies have been designed and investigated using MATLAB Simulation. Simulation results were validated using an experimental setup.

A three-phase transformer based T-type topology for DSTATCOM application

ABSTRACT Among the various reduced switch count multilevel inverter (RSC-MLI) topologies, T-type is the simplified configuration with appreciable reduction in switch count and, posses an ability to serve an alternative to cascaded H-bridge (CHB) MLI. However, extreme reduction in switch count of T-type topology has limited its switching redundancies and created critical dc-link voltage balancing issues in closed-loop applications. In addition, conventional multi-reference PWM scheme reported for T-type produces poor line-voltage total harmonic distortion (THD). Therefore, in this paper, a five-level T-type topology is presented, which involves only one-third dc source requirement of conventional T-type and CHB. This will greatly reduce the dc-link voltage balancing issues and cost. Further, to improve the harmonic performance of conventional multi-reference PWM, a simple carrier-based modulation scheme is proposed. The open and closed performance on the proposed scheme is validated on Simulink and experimental environment considering five-level T-type configuration. To evaluate the dynamic performance of developed T-type configuration, a three-phase three-wire (3P3W) distributed static compensator (DSTATCOM) application is considered, where its ability to eliminate source current harmonics, reactive power and load unbalance is investigated. To promote the superiority of the developed T-type topology, its cost comparison with conventional T-type and CHB is presented.

Trends and Challenges in Multi-Level Inverter with Reduced Switches

Multilevel inverter had been paid a lot of attention from the academia and research community in recent times due to its role in high and medium power applications. In this paper, a detailed survey is made on the recently designed multilevel inverter to find the suitability of the inverters for particular applications. Research is performed on various types of multilevel inverters such as: Symmetric, asymmetric, hybrid and modularized multilevel inverter in order to identify the issues in generating more levels at the output. A summary of various issues in multilevel inverter with reduced switch count is provided, so that a novel topology of multilevel inverter can be designed in future. Further, an 81-level switched ladder multilevel inverter using unidirectional and bidirectional switches is designed. Simulation work is carried out using Matlab/Simulink in order to validate the performance of the inverter with change in resistive load and impedance load. The output of the 81-level inverter is fed to a 110 V, 186.5 W single phase induction motor in order to study the characteristics, further speed control of motor is performed by varying the input voltage of the motor and the results are presented.

Implementation and Analysis of a 15-Level Inverter Topology With Reduced Switch Count

Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve switches and four dc voltage sources to produce a 15-level staircase output voltage waveform. The objective is to reduce the harmonic in the output voltage and thereby reducing the cost of filter requirement and maintaining high efficiency throughout the operating range. Control of output voltage has been done using the Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation and hardware implementation of the topology under different loads and dynamic conditions are presented to validate the robust performance.

A Survey on Reduced Switch Count Multilevel Inverters

An efficient and cost-effective power converter is a pre-requisite for the modern power applications. With the evolvement of matured medium power self-commutated switching devices, multilevel inverters (MLIs) are emerged as a promising solution for high-power medium-voltage applications. Though, MLIs are performing a promising role in industrial applications, their high device count, size, cost and control complexities have restricted their market penetration. To address the disadvantages of MLIs, researchers are continuously contributing to new generation topologies under the name of reduced switch count (RSC) MLIs. From the past decade, numerous RSC-MLIs topologies have been reported for various applications. Therefore, this paper presents a comprehensive review and classification of RSC-MLI topologies, in terms of their structure, features, limitations, suitability and selection for specific applications.

A Four-Switch Five-Level Inverter

This article introduces a new single-phase five-level inverter with reduced switch count, composed by a coupled-inductor, four switches, and two diodes. Its detailed analysis is provided, including a space-vector pulsewidth modulation strategy and design of its components. Compared with the conventional three-level neutral-point clamped (NPC) inverter, the introduced converter generates an output waveform with five levels, while having the same number of devices. In addition, the topology uses less components and has lower conduction losses than other existing five-level inverters. The reduced number of devices leads to a fewer number of gate drives, decreasing the cost and complexity of the system. Simulation and experimental results validate the theoretical analysis of the introduced inverter.

A Novel Asymmetrical 21-Level Inverter for Solar PV Energy System With Reduced Switch Count

This article presents a novel asymmetrical 21-level multilevel inverter topology for solar PV application. The proposed topology achieves 21-level output voltage without H-bridge using asymmetric DC sources. This reduces the devices, cost and size. The PV standalone system needs a constant DC voltage magnitude from the solar panels, maximum power point tracking (MPPT) technique used for getting a stable output by using perturb and observe (P&O) algorithm. The PV voltage is boosted over the DC link voltage using a three-level DC-DC boost converter interfaced in between the solar panels and the inverter. The inverter is tested experimentally with various combinational loads and under dynamic load variations with sudden load disturbances. Total standing voltage with a cost function for the proposed MLI is calculated and compared with multiple topologies published recently and found to be cost-effective. A detailed comparison is made in terms of switches count, and sources count, gate driver boards, the number of diodes and capacitor count and component count level factor with the same and other levels of multilevel inverter and found to be the proposed topology is helpful in terms of its less TSV value, devices count, efficient and cost-effective. In both simulation and experimental results, total harmonic distortion (THD) is observed to be the same and is lower than 5% which is under IEEE standards. A hardware prototype is implemented in the laboratory and verified experimentally under dynamic load variations, whereas the simulations are done in MATLAB/Simulink.

Sliding mode controller for extraction and supply of photovoltaic power using switched series parallel sources reduced switch count multilevel inverter

The reduced switch count multilevel inverter (RSC-MLI) is the latest trend in power electronic converters due to reduction in the switch count and cost. However, a large number of RSC-MLIs have not yet reached to the application level because of the absence of modularity, unequal load-sharing among DC sources and the absence of switching redundancies. On the other hand, multilevel dc-link (MLDCL) and switched series parallel sources (SSPS) RSC-MLI topologies are modular structures with adequate switching redundancies and can be an alternative to conventional cascaded H-bridge (CHB) for grid-connected photovoltaic (PV) systems. Therefore, in this paper, a comprehensive comparison among CHB, MLDCL and SSPS topologies has been carried out for grid connected PV application. Based on the outcome, an asymmetric 11 kV three-phase 11-level SSPS RSC-MLI is chosen. In this combination, a common non-linear sliding mode controller (SMC) is developed for generating maximum PV power from asymmetric single-stage PV sources by linearizing the non-linear PV system using an effective feedback linearization scheme. The PV power extracted is delivered to the grid by controlling SSPS RSC-MLI using another SMC. The performance of the system under wide variations of insolation levels is verified in MATLAB and further validated in hardware-in-the-loop OPAL-RT controller.

Design and Experimental Verification of a Single-Phase Asymmetric Hybrid Multi-level Inverter

In recent years, multi-level inverters have emerged as a feasible power conversion solution for medium and high power applications due to better harmonic performance and ability to operate at high voltage/power when compared to traditional two-level inverters. Since the output level of the multi-level inverters depends on the number of the switching elements, as more levels are required, more switching elements are used. This situation makes the circuit and the control design complex and the losses to upsurge. To overcome these limitations and produce low harmonic content at the output, reduced switch count topologies are popular. In this study, a single-phase asymmetric hybrid multi-level inverter is proposed by combining diode clamped and cascaded H-bridge topologies. The inputs of the proposed inverter are selected as two unequal DC voltage sources. In this regard, fewer switching elements are used to obtain the same number of voltage levels at the output when compared to traditional multi-level inverters. The efficiency and the harmonic performance of the proposed topology is both verified by simulation and experimental studies. The gating signals of the semiconductor switches are produced by phase disposition pulse width modulation with carriers’ frequency of 4 kHz. It is shown by the experiments that a maximum efficiency of 94 % and a total harmonic distortion of 29 % are attained in the case studies.