Abstract
An efficient and cost-effective power converter is a pre-requisite for the modern power applications. With the evolvement of matured medium power self-commutated switching devices, multilevel inverters (MLIs) are emerged as a promising solution for high-power medium-voltage applications. Though, MLIs are performing a promising role in industrial applications, their high device count, size, cost and control complexities have restricted their market penetration. To address the disadvantages of MLIs, researchers are continuously contributing to new generation topologies under the name of reduced switch count (RSC) MLIs. From the past decade, numerous RSC-MLIs topologies have been reported for various applications. Therefore, this paper presents a comprehensive review and classification of RSC-MLI topologies, in terms of their structure, features, limitations, suitability and selection for specific applications.
Highlights
The idea of reducing the switch count in inverters was originated in 1996 by proposing a low power bidirectional dclink inverters with a total of eight switches for motor drive application [1]
The continuous evolution of highperformance semiconductor devices has motivated the creation of various research trends in inverters, such as multilevel inverters (MLIs) [2]–[7]
reduced switch count (RSC)-MLI: BACKGROUND The objective of RSC-MLIs is to overcome the limitations of classical MLIs in terms of their size and complexity
Summary
The idea of reducing the switch count in inverters was originated in 1996 by proposing a low power bidirectional dclink inverters with a total of eight switches for motor drive application [1]. A comparison has been made among all the reported topologies in-terms of their structural and operational features such as device count, device ratings, device blocking voltages, power distribution, redundant switching states, utilization of input dc-sources, modularity, fault tolerant ability and generalization to higher levels. This facilitates selection of a well-informed topology for any given application. Future trends and conclusions of the paper are given in Section-V and VI
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