Reduced Surface Field Structure Research Articles

An Efficient Automatic Structure Design Method of Silicon-on-Insulator Lateral Power Device Considering RESURF Constraint

Reduced surface field (RESURF) technology is one of the most common design optimization criteria of silicon-on-insulator (SOI) lateral power devices. This article proposes a RESURF lateral power device design method using a constrained Bayesian optimization (CBO) framework. By casting the task as a constrained optimization problem, the proposed approach can automatically generate a RESURF structure that meets given breakdown voltage (BV) and ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) specifications. The optimization scheme is equipped with two features that can improve the design quality and efficiency. First, design thresholds are used as a safety margin to further assist in reaching the target performance. Second, a model initialization sampling scheme is proposed to guide the sample selection efficiently during initialization steps. Numerical results show that the optimized designs can achieve fully depleted conditions when the breakdown occurs at N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> N junction and in the body while avoiding the p-n junction breakdown. Additionally, they also show that 1) superior designs can be achieved by introducing the design thresholds and 2) model initialization can boost the efficiency of the optimization model.

Modeling and Analysis of 3-D Core-Shell Superjunction Structures

Conventional superjunction (SJ) structures are composed of p- and n-type doped pillars extending longitudinally as linear stripes (LSs). The reduced surface field (RESURF) effect in these structures is essentially due to a 2-D depletion. A 3-D RESURF is expected to be better than a 2-D RESURF and may further improve the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {BV}-\text {R}_{\text {DS}{(} \text {on} {)},\text {sp}}$ </tex-math></inline-formula> tradeoff for SJ devices. A natural 3-D RESURF structure is a core-shell (CS) SJ structure with a cylindrical unit cell. To identify and leverage the advantages that a 3-D RESURF can offer, the CS SJ is theoretically and numerically analyzed in this article. We develop an analytical model that results in closed-form expressions for the electric field profiles in both CS and LS structures. A very close agreement is observed between the analytical results and numerical simulations. The efficacy of 2-D and 3-D RESURF is compared using the model, and it is found that neither of these designs is universally better. The superior design is determined by the fabrication technology limitations. For trench refill type technologies, the CS design can offer substantial improvement, but, for lithography limited technologies, the CS design shows a significant deterioration in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {BV}-\text {R}_{\text {DS}{(} \text {on} {)},\text {sp}} $ </tex-math></inline-formula> tradeoff compared with the LS design.

High‐Breakdown‐Voltage AlGaN Channel High‐Electron‐Mobility Transistors with Reduced Surface Field Technique

In this article, reduced surface field (RESURF) AlGaN channel high‐electron‐mobility transistors (HEMTs) are proposed and investigated through 2D simulation for the first time. p+ doping is designed to form the RESURF structure, and the impact of the p+ doping density and length on breakdown characteristics is investigated. The breakdown voltage (BV) can be improved from 819 V for a conventional HEMT to 1746 V for a RESURF HEMT with a p+ doping density of 5 × 1018 cm−3 and length of 4 μm. Although the specific on‐resistance (RON) increases from 1.45 to 2.16 mΩ cm2, the power figure of merit (FOM) increases from 2.49 × 108 to 8.28 × 108 V2 Ω−1 cm−2 by utilizing a RESURF structure. By increasing the Al component of the RESURF AlGaN channel HEMT, the BV can be improved from 1746 to 2199 V. However, the RON also increases from 3.68 to 8.04 mΩ cm2, which leads to a decreasing of the power FOM. Simulation and analysis suggest that RESURF AlGaN channel HEMTs have great potential in power electronic applications.

DC Characteristics Optimization of a Double G-Shield 50 V RF LDMOS

An N-type 50 V RF LDMOS with a RESURF (reduced surface field) structure of dual field plates (grounded shield, or G-shield) was investigated. The effect of the two field plates and N-drift region, including the junction depth and dopant concentration, on the DC characteristics was analyzed by employing the Taurus TCAD device simulator. A high BV (breakdown voltage) can be achieved while keeping a lowRDSON(on-resistance). The simulation results show that the N-drift region dopant concentration has an obvious effect on the BV andRDSONand the junction depth affected these values less. There is an optimized length for the second field plate for a given dopant concentration of the N-drift region. Both factors should be optimized together to determine the best DC characteristics. Meanwhile, the effect of the first field plate on the BV andRDSONcan be ignored. According to the simulation results, 50 V RF LDMOS with an optimized RESURF structure of a double G-shield was fabricated using 0.35 µm technologies. The measurement data show the same trend as the TCAD simulation, where a BV of 118 V andRDSONof 26 ohm·mm were achieved.

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

A low specific on-resistance ( \(R_{{{\rm \mathrm{{\scriptstyle ON}},sp}}}\) ) silicon-on-insulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFF-state, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low \(R_{\rm {\scriptstyle {ON,SP}}}\) and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and \(R_{\rm {\scriptstyle {ON,SP}}}\) . Compared with the p-top SOI pLDMOS, the proposed device reduces the \(R_{\rm {\scriptstyle {ON,SP}}}\) by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail.

High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.

Electrical Characteristic Investigation on a Novel Double-Well Isolation Structure in 600-V-Class High-Voltage Integrated Circuits

In order to achieve a high breakdown voltage (BV) and to avoid local breakdown in high-voltage integrated circuits, a novel double-well (DW) high-voltage divided reduced surface field (RESURF) isolation structure featuring two slender N-well regions located at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{N}^{-}$</tex></formula> -well region is proposed for the first time. The breakdown mechanisms are investigated by theoretical analysis and experimental measurements. In the high-voltage blocking state, the N-well regions can efficiently prevent the P-well region from depleting with the high-side region, so as to maintain the charge balance of the novel isolation structure, which leads to an increase in the BV from 656 V in the conventional isolation structure to 760 V in the proposed structure. The dependence of the electrical characteristics of the isolation on the structure parameters has been analyzed in detail. The novel DW divided RESURF structure has been fabricated in 0.5- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu\hbox{m}$</tex></formula> bipolar–CMOS–DMOS technology, which has verified the feasibility and validity of the new concept.

Novel SOI double-gate MOSFET with a P-type buried layer

An ultra-low specific on-resistance (Ron,sp) integrated silicon-on-insulator (SOI) double-gate triple RESURF (reduced surface field) n-type MOSFET (DG T-RESURF) is proposed. The MOSFET features two structures: an integrated double gates structure (DG) that combines a planar gate with an extended trench gate, and a p-type buried layer (BP) in the n-type drift region. First, the DG forms dual conduction channels and shortens the forward current path, so reducing Ron,sp. The DG works as a vertical field plate to improve the breakdown voltage (BV) characteristics. Second, the BP forms a triple RESURF structure (T-RESURF), which not only increases the drift doping concentration but also modulates the electric field. This results in a reduced Ron,sp and an improved BV. Third, the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP. The BV of 325 V and Ron,sp of 8.6 m Ω·cm2 are obtained for the DG T-RESURF by simulation. Ron,sp of DG T-RESURF is decreased by 63.4% in comparison with a planar-gate single RESURF MOSFET (PG S-RESURF), and the BV is increased by 9.8%.

A charge allocating model for the breakdown voltage calculation and optimization of the lateral RESURF devices

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration (per unit area) of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.

Lateral 4H-SiC MOSFETs with Low On-Resistance by Using Two-Zone Double RESURF Structure

4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.

4H–SiC Lateral Double RESURF MOSFETs With Low on Resistance

Designing and fabrication of 4H-SiC (0001) lateral MOSFETs with a double reduced surface field (RESURF) structure have been investigated to reduce ON resistance. In order to achieve high breakdown voltage, a two-zone RESURF structure was also employed in addition to the double RESURF structure. The simulated double RESURF MOSFETs with optimum doses exhibit slightly higher breakdown voltage and lower drift resistance than the simulated single RESURF MOSFETs. The double RESURF structure is attractive to suppress oxide breakdown at gate edge. After the device simulation for dose optimization, the 4H-SiC two-zone double RESURF MOSFETs have been fabricated by using a self-aligned process. The fabricated MOSFET has demonstrated a high breakdown voltage of 1380 V and a low ON resistance of 66 mOmegamiddotcm2 (including a drift resistance of 24 mOmegamiddotcm2). The drift resistance of the fabricated double RESURF MOSFETs is only 50% or even lower than that of the single RESURF MOSFETs