Reduced Power Supply Research Articles

Technology for advanced high-performance microprocessors

This paper describes the development of logic technologies that meet the density, performance, power, and manufacturing requirements for advanced high-performance microprocessors. Aggressive scaling of MOS transistor dimensions along with reduced power supply provide devices with high performance, low power, and good reliability. Multiple layers of planarized aluminum interconnect with high aspect ratios are used to address the increasing importance of interconnect density and performance. Static RAM test vehicles with small 6-transistor cell sizes are used to develop these logic technologies and to provide early demonstrations of yield and performance capabilities. The manufacturing strategy includes development group ownership of the technology from inception to early manufacturing ramp, extensive reuse of prior generation process equipment and modules, and a "copy exactly" methodology to ensure successful process startup and ramp in multiple facilities.

Palmo cell using sampled data log-domain integrators

The authors present the first log domain integrator for programmable analogue sampled data signal processing. This circuit is specific to the implementation of emergent programmable pulse based signal processing systems yielding greater dynamic range, reduced power supply voltage and increased operating frequency. Simulation results demonstrate the validity of the approach.

Multi-gigahertz operation of 3-junction-interferometer-based Josephson latching logic circuits

Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed.

Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN

We present low-power and high-speed algorithms and architectures for complex adaptive filters. These architectures have been derived via the application of algebraic and algorithm transformations. The strength reduction transformation is applied at the algorithmic level as opposed to the traditional application at the architectural level. This results in a power reduction by 21% as compared with the traditional cross-coupled structure. A fine-grained pipelined architecture for the strength-reduced algorithm is then developed via the relaxed lookahead transformation. This technique, which is an approximation of the conventional lookahead computation, maintains the functionality of the algorithm rather than the input-output behavior. Convergence analysis of the proposed architecture is presented and supported via simulation results. The pipelined architecture allows high-speed operation with negligible hardware overhead. It also enables an additional power savings of 39 to 69% when combined with power-supply reduction. Thus, an overall power reduction ranging from 60-90% over the traditional cross-coupled architecture is achieved. The proposed architecture is then employed as a receive equalizer in a communication system for a data rate of 51.84 Mb/s over 100 m of UTP-3 wiring in an ATM-LAN environment. Simulation results indicate that speedups of up to 156 can be achieved with about a 0.8-dB loss in performance.

Back-gated CMOS on SOIAS for dynamic threshold voltage control

The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured.

Friction Factor Reduction by Addition of a Surfactant in the Transport of a Water/Particle Slurry in a Pipe.

This experimental study examines pressure drop due to pipe friction when a surfactant is added to flowing water/particle slurry, with the goal of using the results in order to reduce power supply requirements when transporting slurry by pump, and improve the heat capacity of the transportation fluid. The following results were obtained: (1) Pressure drop for the water/particle slurry containing the surfactant in which particles accounted for about 12% of the fluid volume, was 25--50% smaller than in case of flowing water. (2) When transporting the water/particle slurry containing the surfactant, it is advisable to reduce the velocity and regulate the Reynolds number Re to approximately 3x10 4 . (3) If the particles in the water/particle slurry are replaced by microcapsules that have a thermal energy storage effect due to their latent heat, the heat transported per unit volume of this slurry becomes twice that of plain water, and the required pumping power is reduced to half that of water.

Technology development strategies for the 21st century

Integrated circuit technology has evolved rapidly over the past thirty years, but physical and economic limits are growing challenges. Optical lithography has been pushed beyond limits imagined 10–15 years ago, but should continue to scale for several more generations before X-ray or other approaches are necessary. Transistor delay has been reduced by at least 30% with every new generation and will continue to do so to below 0.1 μm channel lengths. Reducing power supply voltage along with scaling transistor feature size is necessary for both reliability and power considerations. Interconnects are now as important as transistors in determining the performance of logic circuits and will require more layers and new materials to maintain performance and density trends. The increase in technology complexity has brought with it a significant increase in cost, a trend that can not be continued. Cost is now as important a consideration as performance and density in developing integrated circuit technologies.

Friction Factor Reduction by Addition of a Surfactant in the Transport of a Water/Particle Slurry in a Pipe.

This experimental study examines pressure drop due to pipe friction when a surfactant is added to flowing water/particle slurry, with the goal of using the results in order to reduce power supply requirements when transporting slurry by pump, and improve the heat capacity of the transportation fluid. The following results were obtained: (1) Pressure drop for the water/particle slurry containing the surfactant in which particles accounted for about 12% of the fluid volume, was 25--50% smaller than in case of flowing water. (2) When transporting the water/particle slurry containing the surfactant, it is advisable to reduce the velocity and regulate the Reynolds number Re to approximately 3x10 4 . (3) If the particles in the water/particle slurry are replaced by microcapsules that have a thermal energy storage effect due to their latent heat, the heat transported per unit volume of this slurry becomes twice that of plain water, and the required pumping power is reduced to half that of water.

Swhched-current CMOS ternary logic circuits

Abstract A new switched-current CMOS ternary logic family is presented. Circuit descriptions of the basic gates (inverters, NAND, and NOR) are presented and their performance characteristics are evaluated using SPICE simulations. The results obtained indicate that the proposed circuits have good noise margins of about 15% of the power supply voltage, and that the propagation delay is less than 1 ns in most cases. Scaled gates, using the constant field scaling law, are found lo operate efficiently at reduced power supply voltages, down to 1.0 V. A design procedure to implement any ternary logic function using the proposed gates as basic building blocks is also given.

Trends in low-power RAM circuit technologies

Trends in low-power circuit technologies of CMOS RAM chips are reviewed in terms of three key issues: charging capacitance, operating voltage, and dc current. The discussion includes a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs. In DRAMs, successive circuit advancements have produced a power reduction equivalent to two to three orders of magnitude over the last decade for a fixed memory capacity chip. Coupled with the low-power advantage of CMOS circuits, two technologies have been the major contributors to power reduction: lower charging capacitance due to partial activation of multi-divided arrays that use multi-divisions of data and word lines; and lower operating voltage resulting from external power supply reduction, half-V/sub DD/ precharging and on-chip voltage down converting scheme. In SRAMs, partial activation of a multi-divided word line drastically reduces the dc current from the data-line load to the selected cell. In addition to advances in the sense amplifier circuit, an auto power down scheme that uses address transition detection for word driver and column circuitry further reduces the dc current. It is also shown that to design ultralow voltage DRAMs and SRAMs, the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks will be indispensable in the future.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Probing the Limits of Silicon-Based Nanoelectronics

ABSTRACTThe ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.

A wireless volume control receiver for hearing aids

The design of a practical wireless volume-control receiver for hearing aids is proposed in this paper. A trade-off design approach is introduced to solve the problem of minimizing the size of the receiver, reduce its power consumption, and maximize its performance. The receiver decodes standard dual-tone multifrequency (DTMF) signals and it requires only one multiplexed switched capacitor bandpass filter. Another unique component is the OTA design in weak inversion with reduced power supply, high voltage gain, and micropower dissipation. Most of the signals are processed using digital logic which contributes to the simplicity and power efficiency of the design. The IC layout of the receiver measures 1918 /spl mu/m/spl times/1109 /spl mu/m and it was implemented in a 2 /spl mu/m CMOS technology with a 0.5 V threshold voltage. Experimental results using discrete (commercial) components show that the receiver can detect each valid frequency within 0.41% of the nominal value. A modified version of the receiver may be used as a DTMF decoder. This approach has also been used to design a wireless programmable interface for hearing aids.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

An experimental 2.0-volt low-power PowerPC 601™ Microprocessor built in a modified 3.6-volt, 0.6-µm IBM CMOS technology is described. By using unmodified tasks from the 3.6-volt design, a 3× power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power market while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are deuced or eliminated. Challenges to this technique include I/O interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, a long with the experimental changes. The paper reviews the motivation behind low-power microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction.

Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation

In this paper, we present a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 /spl Aring/ and 130 /spl Aring/, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. This model, based on hole injection from the anode, accurately predicts Q/sub BD/ and t/sub BD/ behavior including a fluence in excess of 10/sup 7/ C/cm/sup 2/ at an oxide voltage of 2.4 V for a 25 /spl Aring/ oxide. Moreover, this model is a refinement of and fully complementary with the well known 1/E model, while offering the ability to predict oxide reliability for low voltages. >

Device characterisation of a high-performance 0.25 μm CMOS technology

The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were obtained. Hot carrier degradation experiments showed that NMOS devices could operate at 2.5 V supply voltage. The delay per stage of a non-optimized 51-stage ringoscillators fabricated in the 0.25 μm process was 62 ps at 2.5 V supply voltage which is a 1.5 times improvement over the delay obtained in a 0.5 μm CMOS technology at 3.3V.

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

A high-performance 0.25- mu m-channel CMOS technology is designed and characterized. The technology utilizes n/sup +/ polysilicon gates on nFETs and p/sup +/ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, C/sub w/=0.2 pF) delay per stage of 280 ps at W/sub eff//L/sub eff/=15 mu m/0.25 mu m, which is a 1.7* improvement over 0.5- mu m CMOS technology. At a channel length of 0.18 mu m, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed. >

Future trends in BiCMOS technology

BiCMOS provides CMOS power and densities at Bipolar speeds. At a given technology level, BiCMOS out performs CMOS by a factor of 1.5–2.0X. A 0.8μ BiCMOS technology exceeds the performance of a sub-0.5μm CMOS technology. This has been demonstrated in applications ranging from SRAMs to microprocessors. The main disadvantage of BiCMOS is process complexity, which results in a 1.1–1.3X packaged chip cost. Now that BiCMOS has been demonstrated at 0.5μm, the challenge has shifted from process and technology to circuits and systems. The role of BiCMOS in a reduced power supply environment is still controversial. Two approaches are being taken to resolve the speed degradation of the conventional BiCMOS buffer at 3.3V. On-chip voltage regulation is being used to operate sub-0.5μm CMOS at lower fields, while maintaining the I/O at standard 5V levels. The second approach replaces conventional BiCMOS buffers with new logic gates capable of operating below 3V. It follows that BiCMOS technology will extend the use of TTL & ECL interfaces into the deep sub-micron regime. Both digital and digital-analog systems will exploit these advanced BiCMOS technologies.

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8- mu m BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Endurance of MOSFETs with rapid thermally reoxidized nitrided thin gate oxides to hot carrier-induced GIDL

Summary form only given. The authors report a complete investigation of the off-state degradation in MOSFETs with rapid thermally nitrided (RTN) and rapid thermally reoxidized nitrided (RTN/RTO) MOSFETs. It is demonstrated that RTN/RTO MOSFETs show the least Delta I/sub d/ for low V/sub d/ (5 V), which makes it a promising replacement for pure oxide, especially in the future reduced power supply operations. The impact of RTN and subsequent RTO on the stress-induced gate-induced drain leakage (GIDL) in MOSFETs was also investigated. RTN/RTO samples were found to show the least Delta I/sub d/ under low V/sub d/. >

Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E/sub c/L/sub eff/, where E/sub c/ is the critical electric field necessary to cause carrier velocity saturation and L/sub eff/ is the effective channel length, is introduced. Experimental results confirmed that 1.1E/sub c/L/sub eff/ predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 mu m). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E/sub c/L/sub eff/ can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6- mu m channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E/sub c/L/sub eff/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>