Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

Abstract

An experimental 2.0-volt low-power PowerPC 601™ Microprocessor built in a modified 3.6-volt, 0.6-µm IBM CMOS technology is described. By using unmodified tasks from the 3.6-volt design, a 3× power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power market while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are deuced or eliminated. Challenges to this technique include I/O interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, a long with the experimental changes. The paper reviews the motivation behind low-power microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction.