Reduced Instruction Set Computer Architecture Research Articles

Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

FPGA Design for Low Delay Comparison-free, Odd-even Merge Sorter

Background/Objective: Reduced Instruction Set Computer (RISC) is one of the most common types of architecture involved in microprocessor that has several blocks. There is a lot of scope that can be observed in optimizing these blocks involved in RISC resulting in better and effective microprocessors. Method: One of the sub-blocks that plays a prominent role in RISC architecture is sorter, and it can be achieved by modifying the sorting algorithm. Findings: A novel odd-even comparison-free sorting that assists in arranging N several data components in roughly N clock cycles is proposed here. N identical blocks are arranged in streamlined manner that are stacked using handful primary logic elements resulting in sorter computation. In the proposed framework, classification and categorization activities are executed in a channeled fashion. The entire design is amalgamated for numerous data sets from imitated indiscriminately generated data elements to all exceptional elements, to all the similar elements, and also from random to completely sorted data elements. It has been observed that, the algorithm appears impartial to the input ordering. Novelty: comparison-free unit was implemented on odd-even sorter. Synthesis results indicate that the proposed approach consumes reasonably low FPGA resource. The number of elements consider for sorting was N=8, this architecture takes per element sorting delay as approximately 2.1 to 4.4 ns (1 clock cycle). Keywords: Comparisonfree technique; Hardware sorting engine; Look ip tables; RISC; Delay

Reduced Instruction Set Computer (RISC): A Survey

Today’s modern machines are designed to process real time problems and to do so designers try to make them more performance efficient but while doing this, the complexity of design also increases. So, to maintain a balance between both we have to manage this complexity. Now, a question arises how can we do this? The answer resides in our own life. For instance, when we have a complex task to do, we often break it down into simpler sub-tasks and then work upon them individually. How well we are able to do this depends upon the efficiency of our brain. Same analogy we can apply to design processor architecture. To further improve the efficiency, RISC methodology can be proven to be a prominent choice. The RISC is a design methodology which plays an important part in modern embedded systems. From our day-to-day applications like mobile phones to some of the world’s fastest supercomputers like FUGAKU, all are based on RISC architecture. With the advancements in the scaling field and reduction in the price of the ICs, the market starts filling with the RISC based processor. This paper is focused on providing a basic idea about RISC Architecture based processor design and laying out a path that one can follow to design their own RISC processor. Also, Power outages in ICs are the major problem in the VLSI industry so various techniques and methods are also discussed that can be used for optimizing power and improving speed. Some of the major applications are also discussed which provide an idea about the extent of applications, RISC based architecture can be designed.

Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages

Many processors have evolved in the past century; Out of which, Reduced Instruction set Computing (RISC) processors are well known for their ease of use. The next in line was the Microprocessor without Interlocked pipelining stages (MIPS) RISC based architecture. Less number of instructions, good amount of registers makes these processors a boon to use. Often times, MIPS processors loose the battle against their contenders due to lack of speed. Hence, there is a sheer necessity in designing a more robust system that has all the advantages of MIPS. Over time, there have been designs that could solve the power drawbacks and the area optimizations. However, performance criterion is mostly neglected. This paper emphasizes on the performance metric of pipelined 32-bit MIPS microprocessor. This processor supports RISC architecture and has been designed under Harvard architecture. Pipelining technique is used to solve the problem of low performance and achieve smaller execution times. The processor has four pipes. Pipes are the structures which store data. Pipes can be viewed as register banks. These pipes are generally used to store the intermediate data. The design contains various modules like ALU, Instruction fetch register, Execution unit, Memory, Program counter (PC). Verilog HDL has been used to implement the design. The software used is Xilinx ISE for design and ISIM simulator has been used for simulation purposes. The applications of this MIPS microprocessor are abundant. MIPS microprocessor can be used to carry out the fundamental tasks and an application specific core/IP/processor can be designed and combined with MIPS. This facilitates in meeting the goals of high performance, lower time-to-market and cost- effectiveness. Some application specific uses can be for music systems, PDA, Image processing etc.

Indicator-based lightweight steganography on 32-bit RISC architectures for IoT security

Embedded devices with highly constrained resources are emerging in numerous application areas which include wireless sensor networks, Radio-Frequency IDentification (RFID) tags, and Internet of Things (IoT). These devices need to typically communicate small payload in the form of text/image/audio for which security is exceptionally essential. Considering the resource limitation on constrained devices, many crypto algorithms and a few stego algorithms have been designed with lightweight properties. Majority of these algorithms have been tested for lightweight property only based on their algorithmic attributes. Conversely, ensuring such lightweight characteristics by analysing their feasibility to reside and run in a constrained environment based on the device’s architectural attribute is inevitable for IoT applications. This paper aims to contribute by proposing an indicator based lightweight Least Significant Bit (LSB) steganography algorithm and to compare it’s algorithmic and device dependent implementation aspects with similar algorithms on popular 32-bit Reduced Instruction Set Computer (RISC) microcontrollers used in IoT platforms. The proposed variable embedding algorithm achieves a Peak Signal to Noise Ratio (PSNR) of over 46 dB with Normalised Cross Correlation (NCC) & Structural Similarity Index Measure (SSIM) being 0.9999 and 0.9998 respectively for an average embedding capacity of 1.5 bits per pixel. In addition to the above mentioned benchmarking parameter results, the Regular & Singular (RS) group and Sample Pair (SP) steganalysis, were also carried out to validate the security level of the proposed algorithm. On analysing the suitability of the proposed algorithm in terms of timing performance and memory requirements by implementing on different IoT hardware, the microcontroller with PIC32 core achieves a higher embedding throughput of over 2.7 Mega bits per second with a smaller memory footprint of less than 2 KB. Finally, the results obtained from the proposed work outperform the microcontroller implementation of stego algorithms reported in the literature.

Rewarded for RISC

ACM A.M. Turing Award recipients David Patterson and John Hennessy developed the "dangerous" idea that software should be simpler so it can be executed more quickly, which evolved into the Reduced Instruction Set Computer architecture.

On Static Binary Translation of ARM/Thumb Mixed ISA Binaries

Code discovery has been a main challenge for static binary translation, especially when the source instruction set architecture has variable-length instructions, such as the x86 architectures. Due to embedded data such as PC (program counter)-relative data, jump tables, or paddings in the code section, a binary translator may be misled to translate data as instructions. For variable-length instructions, once a piece of data is mis-translated as instructions, decoding subsequent bytes could also go wrong. We are concerned with static binary translation for the very popular Advanced RISC Machine (ARM) architectures. Although ARM is considered a reduced instruction set computer architecture, it does allow the mix of 32-bit (ARM) instructions and 16-bit (Thumb) instructions in the same executables. In addition to different instruction lengths, the ARM and Thumb instructions are located at 4-byte or 2-byte aligned addresses, respectively. Furthermore, because ARM and Thumb instructions share the same encoding space, a 4-byte word could sometimes be decoded as one ARM instruction or two Thumb instructions. The correct decoding of this 4-byte word is actually determined at runtime by the least-significant bit of the program counter. For unstripped binaries, the mapping symbols can be used to identify ARM code regions and Thumb code regions. However, for stripped binaries, such mapping symbols are unavailable. We propose a novel solution to statically translate stripped ARM/Thumb mixed executables. Our solution is implemented in a static binary translator. The binary translator further generates multiple versions of translated code for the code regions whose types cannot be determined with our solution. One of the code versions is selected during runtime. The binary translator also includes a series of analyses that enable the removal of most useless code versions. Based on the experimental results on stripped ARM/Thumb mixed binaries in the SPEC2006 and Embedded Microprocessor Benchmark Consortium (EEMBC) benchmark suites, our static binary translator achieves impressive performance when migrating them to run on x86 machines and the space overhead is no more than 10%.

John L. Hennessy risk taker

In the 1980s, John L. Hennessy, then a professor of electrical engineering at Stanford University, shook up the computer industry by taking the concepts of reduced instruction set computing (RISC) to the masses. Hennessy wrote papers, gave talks, designed chips, started companies, and even, literally, wrote the book (a textbook that's still used today). The RISC architecture, which focused on simpler, lower-cost microprocessors, was then thought to be an academic exercise with little practical use; today it plays a major role in the industry. Hennessy, now president of Stanford, is once again designing, testing, and advocating a new architecture, this time in the field of university education. He first began rethinking research at universities and recently began reimagining university education itself.

Contributions to the GNU Compiler Collection

The GCC (GNU Compiler Collection) project of the Free Software Foundation has resulted in one of the most widespread compilers in use today that is capable of generating code for a variety of platforms. Since 1987, many volunteers from academia and the private sector have been working to continuously improve the functionality and quality of GCC. Some of the compiler's key components were, and continue to be, developed at IBM Research laboratories. We review several of IBM's contributions to the compiler, including a code generator for the IBM zSeries® processor and a front end for a PL/I-like language used for systems software programming. We also cover many optimizations, including the interblock instruction scheduler, software pipeliner, and vectorizer. These contributions help improve the overall performance of code generated by GCC, and in particular, enhance the IBM RISC (reduced instruction set computer) architecture and the zSeries processors. This paper includes a report on our general experience with GCC in both open source and proprietary software environments and reviews the quality and performance of GCC-generated code.

Parallelization of the FLAPW method

The FLAPW (full-potential linearized-augmented plane-wave) method is one of the most accurate first-principles methods for determining structural, electronic and magnetic properties of crystals and surfaces. Until the present work, the FLAPW method has been limited to systems of less than about a hundred atoms due to the lack of an efficient parallel implementation to exploit the power and memory of parallel computers. In this work, we present an efficient parallelization of the method by division among the processors of the plane-wave components for each state. The code is also optimized for RISC (reduced instruction set computer) architectures, such as those found on most parallel computers, making full use of BLAS (basic linear algebra subprograms) wherever possible. Scaling results are presented for systems of up to 686 silicon atoms and 343 palladium atoms per unit cell, running on up to 512 processors on a CRAY T3E parallel supercomputer.

An electronic dimming ballast with bifrequency and fuzzy logic control

This paper presents the analysis and design of a series-resonant parallel-loaded inverter applied to electronic dimming ballasts with bifrequency and fuzzy logic control. The analysis of the ballast is carried out in conjunction with the fluorescent lamp represented in a plasma model. The component values of the power stage, as well as two switching frequencies, according to the desired maximum and minimum power levels are, therefore, determined. The power levels in between are controlled by varying the ratio between two time intervals for which the two frequencies last, respectively. This mechanism is achieved by using a fuzzy logic controller (FLC). A ballast prototype with the FLC which is implemented on an 8-bit microprocessor with a reduced instruction set computer architecture has been built. Experimental measurements have shown the feasibility of the ballast with the proposed control strategy.

An Empirical Methodology for Exploring Reconfigurable Architectures

Recent research in reduced instruction set computer architectures has emphasized the importance of the empirical approach to designing computer architectures: architectural features are analyzed for utility and cost with respect to the system software that uses them. This approach has resulted in architectural simulators that allow computer designers to vary the features of the architecture being simulated and to analyze how the addition or removal of these features affects the cost and performance of the architecture. In this paper we apply this technique to a new area: reconfigurable architectures. Our approach is to use an empirical methodology that emphasizes the interaction between the target software and the reconfigurability features of parallel architectures. We have developed a set of tools, the reconfigurable architecture workbench, that assists in this methodology by allowing parallel programs to be simulated on a target architecture in order to study the performance implications of various reconfigurability features. The workbench is based on a framework, the PCI model, which describes the range of parallel programs, parallel architectures, and reconfiguration features. We present details of the design and implementation of a prototype workbench, GT-RAW. GT-RAW is being used to study the utility of one dimension of reconfiguration for image processing and image understanding applications. We present an example of the experiments that are being conducted with GT-RAW as a demonstration of our empirical methodology.

How RISCy is DSP?

The characteristics of benchmark digital signal processing (DSP) algorithms are examined. These characteristics are used to suggest the features of an ideal DSP architecture, which is compared to current DSP and reduced instruction set computer (RISC) architectures. Timing comparisons taken from data books and research show that several on-the-market RISCs have a DSP performance close to or better than some DSP chips. Analysis of these DSP and RISC architectures leads to the suggestion of an ideal low-cost RISC DSP chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A multichip superconducting microcomputer ETL-JC1

A multichip 4-b superconducting microcomputer named ETL-JC1 has been designed based on Josephson LSI technology in order to demonstrate the feasibility of a Josephson computer system. The ETL-JC1 is the first Josephson computer than can execute a computer program stored in the ROM chip. In order to make the ETL-JC1, the following key technologies were developed: an Nb tunnel junction integration process, an LSI logic circuit, memory chips of 1-kb ROM and 1-kb RAM a CAD (computer-aided design) system to develop Josephson LSIs, and a multiphase power supply system. The computer consists of four Josephson LSI chips essential to execute the computer functions of arithmetic-logic, sequence control, program memory, and data memory. The whole computer system was based on a RISC (reduced-instruction-set computer) architecture. The four chips were fabricated using a 3- mu m Nb/Al-oxide/Nb junction integration process. Photomasks for the logic circuits were made by using the CAD system, in which the layout of logic gates on the chip and wiring among them were carried out using a standard-cell method. The 128-step program was executed fully in the ETL-JC1 to test a full set of 27 kinds of basic RISC instructions, memory access, subroutine call/return, and so forth, which are sufficient to make any computer program. The total power dissipation was 6.2 mW in all circuits of the ETL-JC1 consisting of more than 22000 junctions. An operation speed of 1 GIPS (giga-instruction per second) can be expected with single CPU in this system by computer logic simulation.

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit. >

Data-driven array processor for video signal processing

A software approach to digital video signal processing which is based on a programmable array processor that can be used as a building block to construct systems of arbitrary complexity is presented. The processor consists of 16 individually programmable cells with 12-bit RISC (reduced instruction set computer) architectures; the peak performance is 4 GOPS, the maximum data transfer rate across chip boundaries is 750 Mbytes/s. The processor executes statistically scheduled data flow programs. To this end, all communication-whether between cells or between processors-is data-driven (as opposed to clock-driven). Self-timed hardware mechanisms that handle the synchronous data flows automatically and transparently are provided. The technology enables the integration of 1.2 million transistors on a single chip, and clock rates up to 125 MHz. The data flow processor architecture allows the parallelisms inherent in many video applications to be fully exploited; at the same time, the programming task is facilitated through the built-in hardware support for intercell and interprocessor communication.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comparison of RISC architectures

Three new RISC (reduced instruction set computer) architectures, the Intel i860, the Motorola 88000, and the Sun Microsystems Sparc, are compared. The relative importance of an architectural comparison, as opposed to a comparison of implementations, is discussed, followed by a high-level overview of each of the architectures. The relative strengths and weaknesses of the three architectures in a number of key areas are analyzed, and their overall relative strengths and weaknesses are summarized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Macintosh Workstations

Reduced Instruction Set Computer (RISC) processors represent a different way to design a CPU for a workstation. They are not magical elixirs to supercharge a personal computer into a mainframe; rather, they are simply a different approach to handling information. RISC design has already affected the architecture of more traditional CISC (Complex Instruction Set Computer) processors and will continue to do so well into the next decade. Given the wealth of software written for CISC processors and the pau‐city of RISC shaped applications, combined with the usual lag in software development behind any hardware breakthrough, a full‐fledged RISC library workstation may not appear for some time. Nevertheless RISC has earned a great deal of attention since its practical birth at IBM in 1976 by John Cocke and its pursuit in academic circles at Stanford and the University of California, Berkeley in the early 1980s. Bom from the simple idea of devising a way to complete a computer instruction in a single cycle of a processor, RISC architecture has been called the de facto standard of the next decade for workstations by some and a mere fad by others. Will these chips replace CISC processors entirely? Will they have an impact on library workstations? And will they ever appear in one form or another in the Macintosh? With RISC processors available from MIPS Computer Systems, Motorola, and Sun, and RISC‐based computers produced by Apollo, Sun, Everex, Hewlett‐Packard, and others, RISC is certainly a harbinger of the future of processors in workstations. The market for RISC‐based worksta‐tions is heating up as some manufacturers — Sun, DEC, Data General to mention a few — battle for customers by lowering prices and raising performance.

Effective VLSI processor architectures for HLL computers: the RISC approach

The design principles of reduced-instruction-set computer (RISC) architectures as they apply to VLSI implementation for high-level languages (HLLs) are presented. The nature of general-purpose HLL computations is discussed in terms of static and dynamic program measurements, and the HLL features that need efficient support are identified. CISC (complex-instruction-set computer) and RISC approaches to general-purpose HLL computers are outlined, the effects of instruction-set reduction on both code size and execution time are evaluated, and the delayed-jump concept is introduced. The Berkeley RISC architecture is presented as an example.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The ultimate RISC

Reduced instruction set computer (RISC) architectures have attracted considerable interest during the past decade. The ultimate RISC architecture presented here is an extreme yet simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it is useful.