Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages

Abstract

Many processors have evolved in the past century; Out of which, Reduced Instruction set Computing (RISC) processors are well known for their ease of use. The next in line was the Microprocessor without Interlocked pipelining stages (MIPS) RISC based architecture. Less number of instructions, good amount of registers makes these processors a boon to use. Often times, MIPS processors loose the battle against their contenders due to lack of speed. Hence, there is a sheer necessity in designing a more robust system that has all the advantages of MIPS. Over time, there have been designs that could solve the power drawbacks and the area optimizations. However, performance criterion is mostly neglected. This paper emphasizes on the performance metric of pipelined 32-bit MIPS microprocessor. This processor supports RISC architecture and has been designed under Harvard architecture. Pipelining technique is used to solve the problem of low performance and achieve smaller execution times. The processor has four pipes. Pipes are the structures which store data. Pipes can be viewed as register banks. These pipes are generally used to store the intermediate data. The design contains various modules like ALU, Instruction fetch register, Execution unit, Memory, Program counter (PC). Verilog HDL has been used to implement the design. The software used is Xilinx ISE for design and ISIM simulator has been used for simulation purposes. The applications of this MIPS microprocessor are abundant. MIPS microprocessor can be used to carry out the fundamental tasks and an application specific core/IP/processor can be designed and combined with MIPS. This facilitates in meeting the goals of high performance, lower time-to-market and cost- effectiveness. Some application specific uses can be for music systems, PDA, Image processing etc.