Abstract
A software approach to digital video signal processing which is based on a programmable array processor that can be used as a building block to construct systems of arbitrary complexity is presented. The processor consists of 16 individually programmable cells with 12-bit RISC (reduced instruction set computer) architectures; the peak performance is 4 GOPS, the maximum data transfer rate across chip boundaries is 750 Mbytes/s. The processor executes statistically scheduled data flow programs. To this end, all communication-whether between cells or between processors-is data-driven (as opposed to clock-driven). Self-timed hardware mechanisms that handle the synchronous data flows automatically and transparently are provided. The technology enables the integration of 1.2 million transistors on a single chip, and clock rates up to 125 MHz. The data flow processor architecture allows the parallelisms inherent in many video applications to be fully exploited; at the same time, the programming task is facilitated through the built-in hardware support for intercell and interprocessor communication.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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