Reduce Hardware Overhead Research Articles

SPaRre: selective partial replication for concurrent fault-detection in FSMs

We discuss SPaRe: selective partial replication, a methodology for concurrent fault detection in finite state machine (FSMs). The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor that immediately detects errors by comparison to the original FSM. However, instead of duplicating the FSM, SPaRe selects a few prediction functions which only partially replicate it. Selection is guided by the objective of minimizing the incurred hardware overhead without compromising the ability to detect all faults, yet possibly introducing fault-detection latency. SPaRe is nonintrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results indicate that SPaRe achieves significant hardware overhead reduction over both duplication and test vector logic replication (TVLR), a previously reported concurrent fault-detection method. Moreover, as compared to TVLR, SPaRe also reduces the average fault-detection latency for detecting all permanent faults.

A 2.5 - 10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

This paper describes a technique for stabilizing the binary phase detector (PD) gain under various jitter conditions. A dead zone in the phase detector estimates the magnitude of high-frequency data jitter, and the resulting jitter information is used to control the charge-pump current. An alternating edge-sampling (AES) PD reduces hardware overhead by removing possible redundancies in previous dead-zone implementations. A series sense amplifier driven by a single-phase clock helps high-speed data sampling with increased data evaluation time. A dual path voltage-controlled oscillator incorporating dual-loop architecture enables wide-range operation of clock/data recovery circuits with low jitter. Fabricated in a 0.18-/spl mu/m CMOS process, a test transceiver operates from 2.5 to 11.5 Gb/s with a bit-error rate of less than 10/sup -12/ while consuming 540 mW from a 1.8-V supply.

FFT and IMDCT circuit sharing in dab receiver

This paper proposes a circuit-sharing approach to improve efficiency for the key digital audio broadcasting (DAB) techniques, i.e., MPEG1-audio decoding and orthogonal frequency division multiplexing (OFDM). Because OFDM's fast Fourier transform (FFT) requires heavy computational power for implementation, a single butterfly processing element (BPE) is adopted to reduce the chip area required for FFT. Furthermore, by modifying the BPE logical combinational circuit, both IMDCT (inverse modified discrete cosine transform) and FFT functions can be obtained simultaneously from a single VLSI chip. Therefore, the proposed technique reduces hardware overhead, enhances circuit efficiency and significantly reduces the cost of DAB receivers. The proposed circuit is simulated as a VLSI prototype chip using a 0.35 /spl mu/m CMOS process, with a chip area of about 22.09 mm/sup 2/ and a total gate count of approximately 10839 (excluding ROM and RAM).

Circular BIST with state skipping

Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.

Test data compression and decompression based on internal scan chains and Golomb coding

We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chain(s) of the core under test and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The major advantages of Golomb coding of test data include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. The use of the internal scan chain for decompression obviates the need for a CSR, thereby reducing hardware overhead considerably. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by. applying it to the ISCAS 89 benchmark circuits.

Enhancement of bowel sounds by wavelet-based filtering.

This paper evaluates the performance of an automatic method for structural decomposition, noise removal and enhancement of bowel sounds (BS), based on the wavelet transform. The proposed method combines multiresolution analysis with hard thresholding to compose a wavelet transform-based stationary-nonstationary (WTST-NST) filter, for enhanced separation of bowel sounds (BS) from superimposed noise. Quantitative and qualitative analysis of the experimental results, when applying the WTST-NST filter to BS recorded from controls and patients with gastrointestinal dysfunction, prove that the ability of the WTST-NST filter to remove noise and reveal the authentic structure of BS is excellent. By eliminating the need to record a noise reference signal, this method reduces hardware overhead when analysis of BS is the primary aim. The method is independent of subjective human judgement for selection of noise reference templates, is robust to different levels of signal interference, and, due to its simplicity, can easily be used in clinical medicine.

Self Checking Design Technique for NumericalComputations

The objective of this paper is to develop an efficient method for testing of numerical computations based on algebraic concepts such as transcendental degree of field extensions.A class of polynomially checkable functions is introduced, and for computation of the functions from this class a new method for error detection/error correction is proposed. This class of functions is shown to be large. The proposed method can also be extended to testing of computations of functions which are not polynomially checkable.The preliminary results show great potential of this approach. In particular the proposed approach will lead to substantial reduction in hardware overhead required for multiple error detection and correction, as compare to the check sum method and other existing techniques.

Systematic design of fault-tolerant multiprocessors with shared buses

A multiprocessor system is fault-tolerant (FT) if it preserves a fault-free subsystem of a predetermined interconnection structure when faults appear. We present a new method for designing FT multiprocessors that can efficiently tolerate both processor and interconnection faults. The approach is general, in that it can be applied to any multiprocessor topology. Shared buses serve as the main interconnection mechanism to minimize the switching logic needed for reconfiguration. We employ processor-bus-link (PBL) graphs to model multiprocessors with either dedicated or shared buses. Both processors and buses are represented as nodes so that bus faults can be considered explicitly and tolerated efficiently by spare buses instead of by spare processors. A minimum number of spare processors and buses are used to reduce hardware overhead. The node covering concept and the maximum-weight spanning tree algorithm are then employed to construct FT systems that have lower interconnection cost than most previous designs. We also present a cost-effective implementation method which is suitable for both static and dynamic reconfiguration techniques. The FT systems obtained have the advantages of no critical single point of failure, low redundancy, local replacement, and simple circuitry for fast reconfiguration.

Nonscan design-for-testability techniques using RT-level design information

This paper presents nonscan design-for-testability (DFT) techniques applicable to register-transfer (RT)-level data path circuits. Knowledge of high-level design information, in the form of the RT-level structure, as well as the functions of the RT-level components is utilized to develop effective nonscan DFT techniques. Instead of conventional techniques of selecting flip-flops (FF's) to make systems controllable/observable, execution units (EXU's) are selected using the EXU S-graph introduced in this paper. Controllability/observability points can be implemented using register files and constants. We introduce the notion of k-level controllable and observable loops and demonstrate that it suffices to make all the loops k-level controllable/observable, k>0, to achieve very high test efficiency. The new testability measure eliminates the need by traditional DFT techniques to make all loops directly (zero-level) controllable/observable, reducing significantly the hardware overhead required and making the nonscan DFT approach feasible and effective. We discuss ways of avoiding the formation of reconvergent regions while adding test points to make loops k-level controllable/observable. We introduce dual points, which utilize the different controllability/observability levels of loops, to make one loop controllable while making another loop observable. We present efficient algorithms to add the minimal hardware possible to make all loops in the data path k-level controllable/observable, without the use of scan FF's. The nonscan DFT techniques were applied to several data path circuits. The experimental results demonstrate the effectiveness of the k-level testability measure, and the use of distributed and dual points, to generate easily testable data paths with reduced hardware overhead. The hardware overhead and the test application time required for the nonscan designs are significantly lower than for the partial scan designs. Most significantly, the experimental results demonstrate the ability of the RT-level DFT techniques to produce nonscan testable data paths, which can be tested at-speed.

Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis

Fault-tolerant design of analog circuits is more difficult than that of digital circuits. Chatterjee has proposed a continuous checksum-based technique to design fault-tolerant linear analog circuits. However, hardware overhead of the embedded checker is an important issue in this technique, which has never been addressed before. This paper proposes an algorithm for reduction of hardware overhead in the checker. Without changing the original circuit, the proposed algorithm can not only reduce the number of passive elements, but also the number of analog operators so that the error detection circuitry in the checker has optimal hardware overhead. As the basis of the algorithm, a serial of theoretic results, including the concept and existence conditions of all-non-zero solutions, have also been presented to verify the algorithm.

BOARD LEVEL PARTITIONING FOR IMPROVED PARTIAL SCAN

We present a two phase board level partitioning scheme for improved partial scan on the resulting Integrated Circuits (ICs). The first phase clusters the nodes of the synchronous sequential PCB system into sets of bounded capacity. Each set represents an IC. The main objective function is to minimize the maximum number of inputs to a set. This considerably affects the test generation and response verification phases while testing the ICs. The second phase repositions the flip-flops so that we minimize the partial scan related hardware overhead for each IC, maintain a small sequential depth for all chips, and minimize the period of the global clock. We present an efficient iterative improvement heuristic for the partitioning problem of the first phase whose performance is tested on benchmarks. We also employ provably good algorithms for the second phase which result to reduced hardware overhead for partial scan. The proposed tool may also be applied to the system level partitioning problem where we partition the input circuit into Printed Circuit Boards or Multi-Chip Modules.

Built-in self-test structure for mixed-mode circuits

A built-in self-test (BIST) structure is presented which provides controllability and observability to analog circuits under test with significantly reduced hardware overhead compared to previously reported methods. The test structure is equally applicable to digital circuits, and lends itself to automated insertion into circuits under test. >

A design method for on-line reconfigurable array processors

A design methodology for reconfigurable array processors is described which extends a known design method for non-redundant array architectures. Using self-checking processing elements, the systematic design of on-line reconfigurable arrays is feasible, which perform reconfiguration concurrently with data processing. Reconfiguration schemes suitable for one- and two-dimensional array processors are presented. Another scheme addresses arrays with high probability of dynamic faults while static faults cannot be neglected. Dynamic and static faults are treated differently to reduce hardware overhead. A systematic approach for reliability estimation based on a model including dynamic and static faults is discussed. The design method is applied to matrix-matrix-multiplication. Estimations of hardware overhead are given. >

Analysis of Hamming count compaction scheme

Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique. Since BIST methods use productive chip area, a prime concern is providing the test results using the minimal amount of space. Hardware overhead reduction through counter elimination is considered for the Hamming Count compaction test. Intelligent counter selection is necessary to minimize the impact this hardware reduction has on fault detection. A method for selecting the most advantageous syndrome and input variable counter combination to utilize as a reduced H-count test is introduced. Analysis shows that the proposed method produces an optimal pairing. The paired counters have an aliasing probability which is half an order less than that of an unmodified syndrome test with exhaustive inputs. Adaptations in the counter selection method are made using a greedy strategy for choosing multiple counters to combine with the syndrome counter.

Feedback-testing by using multiple input signature registers

In this article, the use of Multiple Input Signature Registers (MISRs) as random pattern generators is investigated. This additional function helps to reduce hardware overhead and testing time, when BIST (Built-In Self-Test) structures are integrated on the chip, because the MISR can at the same time generate test patterns and collect test responses. A formula is presented, which determines the number of clock cycles needed to generate a given number of random patterns. Finally we suggest a method for how the number of test patterns can be reduced when the MISR acts as test pattern generator and compressor in a feedback loop.