BOARD LEVEL PARTITIONING FOR IMPROVED PARTIAL SCAN

Abstract

We present a two phase board level partitioning scheme for improved partial scan on the resulting Integrated Circuits (ICs). The first phase clusters the nodes of the synchronous sequential PCB system into sets of bounded capacity. Each set represents an IC. The main objective function is to minimize the maximum number of inputs to a set. This considerably affects the test generation and response verification phases while testing the ICs. The second phase repositions the flip-flops so that we minimize the partial scan related hardware overhead for each IC, maintain a small sequential depth for all chips, and minimize the period of the global clock. We present an efficient iterative improvement heuristic for the partitioning problem of the first phase whose performance is tested on benchmarks. We also employ provably good algorithms for the second phase which result to reduced hardware overhead for partial scan. The proposed tool may also be applied to the system level partitioning problem where we partition the input circuit into Printed Circuit Boards or Multi-Chip Modules.