Abstract
In this article, the use of Multiple Input Signature Registers (MISRs) as random pattern generators is investigated. This additional function helps to reduce hardware overhead and testing time, when BIST (Built-In Self-Test) structures are integrated on the chip, because the MISR can at the same time generate test patterns and collect test responses. A formula is presented, which determines the number of clock cycles needed to generate a given number of random patterns. Finally we suggest a method for how the number of test patterns can be reduced when the MISR acts as test pattern generator and compressor in a feedback loop.
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