Reduce Hardware Overhead Research Articles

SET-detection low complexity burst error correction codes for SRAM protection

As the feature size of transistors decreases, multiple bit upsets and single event transient effects become severe in circuits working in radiation environment. In static random-access memories (SRAM), both single event upsets and single event transients need caring about. Fault-tolerant ECCs are optional for SRAM protection, which own the ability to deal with SEU and SET at the same time. We designed a series of low complexity burst error correcting codes with fault detection feature. This can deal with burst errors in memories and transient errors in the decoder. Low complexity ECC simplifies the decoding circuits and reduces hardware overhead. Compared with schemes to deal with SET in decoders, the proposed scheme has obvious advantage on area’s overhead and can be an effective choice for SRAM protection in radiation environment.

LPHD: A low power and high diffusion lightweight block cipher

AbstractSmart door locks pose a large number of threats such as network attacks. Its storage area and power of cipher are severely limited because the wireless nodes of smart door locks are mostly battery‐powered. Therefore, effective security solutions are urgently needed. In this paper, a new lightweight block cipher with low power named LPHD is proposed to ensure the security of the master control chip of the smart door lock terminal. We design a scheme of low power S‐box and construct the two‐stage permutation layer (TP structure) suitable for LPHD by filtering the sets of 8‐bit permutations. LPHD proposes a variant of the 8‐branch generalized Feistel structure (GFS) to realize that the bits of all branches are affected in one encryption round. The problem of slow diffusion in the standard Feistel structure is solved. The key schedule adopts the nonlinear design and reuses the encryption process of LPHD. It improves the security of the cipher and reduces hardware overhead. Moreover, we evaluate the hardware implementation and security of LPHD. The results show that LPHD for the unified encryption and decryption circuits requires only 1276 Gate Equivalents (GEs) and 1.914 W on UMC 0.18 m, which is better than other lightweight block ciphers such as SKINNY, PRESENT, and IVLBC. In summary, LPHD provides sufficient security for the master control chip of the smart door lock terminal.

Ferroelectric-defined reconfigurable homojunctions for in-memory sensing and computing.

Recently, the increasing demand for data-centric applications is driving the elimination of image sensing, memory and computing unit interface, thus promising for latency- and energy-strict applications. Although dedicated electronic hardware has inspired the development of in-memory computing and in-sensor computing, folding the entire signal chain into one device remains challenging. Here an in-memory sensing and computing architecture is demonstrated using ferroelectric-defined reconfigurable two-dimensional photodiode arrays. High-level cognitive computing is realized based on the multiplications of light power and photoresponsivity through the photocurrent generation process and Kirchhoff's law. The weight is stored and programmed locally by the ferroelectric domains, enabling 51 (>5 bit) distinguishable weight states with linear, symmetric and reversible manipulation characteristics. Image recognition can be performed without any external memory and computing units. The three-in-one paradigm, integrating high-level computing, weight memorization and high-performance sensing, paves the way for a computing architecture with low energy consumption, low latency and reduced hardware overhead.

A configurable hardware-efficient ECG classification inference engine based on CNN for mobile healthcare applications

—Electrocardiogram (ECG) processors for healthcare have been widely used, however most of them can only adapt to specific applications, lacking flexibility. For achieving scalable on-chip ECG classification, a flexible inference engine based on one-dimensional (1-D) convolutional neural network (CNN) is proposed. By utilizing the proposed computing strategy based on systolic arrays, filter level parallelism and output channel parallelism are achieved. The configurable processing units (PUs) and modifiable instruction registers allow this inference engine to support computing of 1-D convolutional layers or fully connected layers with different scales. Based on the proposed data buffers system with multi-level storage structure, the input feature values and weight values are reused, thereby reducing hardware overhead and memory access power. This design has been validated on FPGA using our proposed two arrhythmia classification models that represent low energy consumption and high accuracy requirements, achieving accuracy of 98.9% and 99.3%, respectively, with energy consumption of 2.05 μJ and 14.27 μJ per classification at 200 MHz. The hardware implementation results indicate that good configurability enables our design to adapt to different ECG classification scenarios, effectively improving the hardware universality in mobile healthcare applications.

Sparse matrix multiplication in a record-low power self-rectifying memristor array for scientific computing.

Memristor-enabled in-memory computing provides an unconventional computing paradigm to surpass the energy efficiency of von Neumann computers. Owing to the limitation of the computing mechanism, while the crossbar structure is desirable for dense computation, the system's energy and area efficiency degrade substantially in performing sparse computation tasks, such as scientific computing. In this work, we report a high-efficiency in-memory sparse computing system based on a self-rectifying memristor array. This system originates from an analog computing mechanism that is motivated by the device's self-rectifying nature, which can achieve an overall performance of ~97 to ~11 TOPS/W for 2- to 8-bit sparse computation when processing practical scientific computing tasks. Compared to previous in-memory computing system, this work provides over 85 times improvement in energy efficiency with an approximately 340 times reduction in hardware overhead. This work can pave the road toward a highly efficient in-memory computing platform for high-performance computing.

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store

The separation of memory and arithmetic logic unit (ALU) in the von Neumann computing architecture hinders the development of big data and high-performance computing. In-memory computing (IMC) as a new computation method significantly reduces the latency and power consumption of data processing. In this study, we propose a fully digital static random access memory (SRAM)-based IMC architecture, which has the following advantages: 1) it simplifies multiplication to multicycle addition operations, reuses logic cells, and reduces hardware overhead; 2) by adding a pair of nMOS transistors to achieve internal write-back, the computational efficiency is improved, and at the same time, the final result of the multiplication can be stored locally, eliminating the need to read the computational result immediately; and 3) this scheme can be easily expanded to multiplication operations with different bit widths, which provides good scalability. A 4-kb SRAM-IMC macro chip is manufactured using the SMIC 55-nm technology to realize 4-bit multiplication, with an energy efficiency of 51.4 TOPS/W (0.9 V) and a throughput of 234.3 GOPS/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . The proposed multiplication–accumulation architecture is applied to a neural network, which achieves 98.7% accuracy with the Mixed National Institute of Standards and Technology database (MNIST) dataset.

침투 공격 검출을 위한 비대칭 신호 스캐닝 기법

Design-For-Security (DFS) methodology is to protect integrated circuits from physical attacks, and that can be implemented by adding a security circuit to detect abnormal external access. Among the abnormal accesses called invasive attack, microprobing and FIB circuit editing are classified as the most powerful methods because they have direct access. Microprobing deliberately inject defects into the wire of circuit through probes, or reads and changes data. FIB circuit editing is methods of reconnecting or destroying circuits to neutralize security circuits or to access data. Previous DFS methodology have responded to the attacks by detecting arrival time asymmetry between the two signals or by comparing input/output data based on encrypted communication. This study conducted to reduce hardware overhead, and the proposed circuit detects the reflected signal asymmetry generated through probe or FIB circuit editing and detects the attacks through comparison. Since the proposed security circuit reduces the size and test cycle of the circuit compared to previous studies, the cost used for security can be reduced.

Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((22)2)2), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm2, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously.

SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme.

Deep neural networks have been deployed in various hardware accelerators, such as graph process units (GPUs), field-program gate arrays (FPGAs), and application specific integrated circuit (ASIC) chips. Normally, a huge amount of computation is required in the inference process, creating significant logic resource overheads. In addition, frequent data accessions between off-chip memory and hardware accelerators create bottlenecks, leading to decline in hardware efficiency. Many solutions have been proposed to reduce hardware overhead and data movements. For example, specific lookup-table (LUT)-based hardware architecture can be used to mitigate computing operation demands. However, typical LUT-based accelerators are affected by computational precision limitation and poor scalability issues. In this paper, we propose a search-based computing scheme based on an LUT solution, which improves computation efficiency by replacing traditional multiplication with a search operation. In addition, the proposed scheme supports different precision multiple-bit widths to meet the needs of different DNN-based applications. We design a reconfigurable computing strategy, which can efficiently adapt to the convolution of different kernel sizes to improve hardware scalability. We implement a search-based architecture, namely SCA, which adopts an on-chip storage mechanism, thus greatly reducing interactions with off-chip memory and alleviating bandwidth pressure. Based on experimental evaluation, the proposed SCA architecture can achieve 92%, 96% and 98% computational utilization for computational precision of 4 bit, 8 bit and 16 bit, respectively. Compared with state-of-the-art LUT-based architecture, the efficiency can be improved four-fold.

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates the All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61%. With ± 20% supply voltage and 5°C to 105°C temperature variations, the All-Spin PUF shows a strong resiliency. In comparison with state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of the All-Spin PUF against emerging modeling attacks is verified as well.

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

Graphics Processing Units (GPUs) are increasingly adopted in several domains where reliability is fundamental, such as self-driving cars and autonomous systems. Unfortunately, GPU devices have been shown to have a high error rate, while the constraints imposed by real-time safety-critical applications make traditional (and costly) replication-based hardening solutions inadequate. This work proposes an effective methodology to identify the architectural vulnerable sites in GPUs modules, i.e., the locations that, if corrupted, most affect the correct instructions execution. We first identify, through an innovative method based on Register-Transfer Level (RTL) fault injection experiments, the architectural vulnerabilities of a GPU model. Then, we mitigate the fault impact via selective hardening applied to the flip-flops that have been identified as critical. We evaluate three hardening strategies: Triple Modular Redundancy (TMR), Triple Modular Redundancy against SETs ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula> TMR), and Dual Interlocked Storage Cells (Dice flip-flops). The results gathered on a publicly available GPU Model (FlexGripPlus) considering functional units, pipeline registers, and warp scheduler controller show that our method can tolerate from 85% to 99% of faults in the pipeline registers, from 50% to 100% of faults in the functional units and up to 10% of faults in the warp scheduler, with a reduced hardware overhead (in the range of 58% to 94% when compared with traditional TMR). Finally, we adapt the methodology to perform a complementary evaluation targeting permanent faults and identify critical sites prone to propagate fault effects across the GPU. We found that a considerable percentage (65% to 98%) of flip-flops that are critical for transient faults are also critical for permanent faults.

Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing

Neural network (NN) computing contains a large number of multiply-and-accumulate (MAC) operations. The performance of NN accelerator is limited with the traditional von Neumann architecture due to the tremendous off-chip memory accesses. Resistive random-access memory (ReRAM)-based crossbars can naturally perform matrix–vector multiplication (MVM) operations and are well suitable for NN accelerators. In the existing ReRAM-based NN accelerators, the synaptic weights represented by the conductances of ReRAMs are mainly based on the binary coding. However, the imperfect fabrication process combined with stochastic filament-based switching leads to resistance variations of ReRAMs, which can significantly alter the weights in binary synapses and degrade the NN accuracy. Moreover, the NN accuracy further deteriorates with multilevel cells (MLCs) used for reducing hardware overhead. In this article, a novel unary coding of synaptic weights is proposed to overcome the resistance variations of MLCs and achieve reliable ReRAM-based neuromorphic computing. A variation-aware optimal mapping scheme is also proposed in compliance with the unary coding to guarantee high accuracy by leveraging a unique feature of unary coding—the existence of multiple ways to represent the same value. The optimal mapping obtains very small errors for weights with resistance variations of MLCs. Our simulation results show that under resistance variations, the proposed method achieves less than 0.08% and 3.43% accuracy loss on CIFAR10 and ImageNet, respectively, compared to the ideal accuracy. With each synaptic weight represented by four 2-b MLCs, the proposed method improves the accuracy over the traditional binary coding scheme by 83.39% and 87.6% for CIFAR10 and ImageNet, respectively.

Resource-Optimized Design of Bit-Shuffle Block Coding for MIMO-VLC

Designing a run-length-limited (RLL) code for a visible light communication (VLC) system requires consideration of several performance factors including hardware overhead, transmission efficiency, and direct current (DC) balance. This paper proposes a novel RLL code called bit-shuffle block codes for high-rate multiple-input multiple-output (MIMO)-VLC systems that can offer excellent constant illumination and transmission efficiency with extensively-optimized hardware resources. Due to the structure of the Omega network, the proposed bit-shuffle block coding method can increase transmission efficiency and significantly reduce hardware overhead. In addition, it can generate codewords dynamically, which guarantees DC balance with multiple LEDs to serve the dual purpose of illumination and communication. Experimental results confirm that the proposed bit-shuffle block coding demonstrate excellent performance in resource optimization, and can be a viable solution for MIMO-VLC applications that can send large volumes data with limited hardware resources.

Exponential suppression of bit-flips in a qubit encoded in an oscillator

A quantum system interacts with its environment, if ever so slightly, no matter how much care is put into isolating it. As a consequence, quantum bits (qubits) undergo errors, putting dauntingly difficult constraints on the hardware suitable for quantum computation. New strategies are emerging to circumvent this problem by encoding a qubit non-locally across the phase space of a physical system. Since most sources of decoherence are due to local fluctuations, the foundational promise is to exponentially suppress errors by increasing a measure of this non-locality. Prominent examples are topological qubits which delocalize quantum information over real space and where spatial extent measures non-locality. In this work, we encode a qubit in the field quadrature space of a superconducting resonator endowed with a special mechanism that dissipates photons in pairs. This process pins down two computational states to separate locations in phase space. As we increase this separation, we measure an exponential decrease of the bit-flip rate while only linearly increasing the phase-flip rate. Since bit-flips are continuously and autonomously corrected at the single qubit level, only phase-flips are left to be corrected via a one-dimensional quantum error correction code. This exponential scaling demonstrates that resonators with non-linear dissipation are promising building blocks for universal fault-tolerant quantum computation with drastically reduced hardware overhead.

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.

Going Deeper in Spiking Neural Networks: VGG and Residual Architectures.

Over the past few years, Spiking Neural Networks (SNNs) have become popular as a possible pathway to enable low-power event-driven neuromorphic hardware. However, their application in machine learning have largely been limited to very shallow neural network architectures for simple problems. In this paper, we propose a novel algorithmic technique for generating an SNN with a deep architecture, and demonstrate its effectiveness on complex visual recognition problems such as CIFAR-10 and ImageNet. Our technique applies to both VGG and Residual network architectures, with significantly better accuracy than the state-of-the-art. Finally, we present analysis of the sparse event-driven computations to demonstrate reduced hardware overhead when operating in the spiking domain.

False history filtering for reducing hardware overhead of FPGA-based LZ77 compressor

Abstract Compression reduces the size of data by replacing original data with shorter bits of code or eliminating unnecessary data, thereby reducing the cost of storing and transmitting data. To reduce CPU load caused by compression, there are many cases where compression is accelerated through parallelization on additional hardware. The higher degree of parallelism leads to a higher processing bandwidth of hardware. However, it also causes a significant increase in hardware resource cost. In this paper, we propose a false history filtering technique that is used by a parallel hardware accelerator to avoid excessive hardware resource cost. This technique detects unnecessary string comparison operations that generate meaningless or unused results. The parallel hardware accelerator with false history filtering has no performance degradation even if the hardware uses less parallelized modules. Experimental results showed that the hardware LZ77 compressor with false history filtering reduces hardware usage by 5.18-18.35% without performance degradation.

An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function

This paper presents a novel microprocessor-based system-on-chip (SoC) with the capability to transform SRAM in the instruction cache to an ambient temperature sensor and a physically unclonable function (PUF). For the transformation, we extend the original microprocessor without interlocked pipeline stages instruction set architecture and update SRAM peripheral circuits and pipeline control. All the changes are made minimally to reduce hardware overhead and the impact on the original microarchitecture. Compared to the conventional approach implementing dedicated hardware for low duty-cycle sensing and PUF, the proposed transformation approach saves ~9.8 $\times $ silicon area while achieving the performance and robustness comparable to the state of the art in implementing those functions. The efficiency of the approach is verified with an SoC prototyped in a 65-nm CMOS.

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation

Built-in redundancy analysis (BIRA) is widely used for memory yield improvement. However, increases in fault occurrence probability inevitably lead to the use of various spare lines to achieve a high repair rate. Generally, it is difficult to apply conventional BIRAs for memories with various spare lines because they focus on a simple spare structure. Therefore, this study examines a BIRA that focuses on a various spare lines structure. The proposed BIRA achieves a high repair rate through the use of various spare lines. Although long analysis time is typically required due to the use of various spare lines, the proposed BIRA solves the problem through sequential spare line allocation. Additionally, it achieves hardware overhead reduction through a simple analyzer. These advantages of the proposed BIRA are demonstrated experimentally.

Partial-DNA cyclic memory for bio-inspired electronic cell

Genome memory is an important aspect of electronic cells. Here, a novel genome memory structure called partial-DNA cyclic memory is proposed, in which cells only store a portion of the system's entire DNA. The stored gene number is independent of the scale of embryonic array and of the target circuit, and can be set according to actual demand in the design process. Genes can be transferred in the cell and the embryonics array through intracellular and intercellular gene cyclic and non-cyclic shifts, and based on this process the embryonic array's functional differentiation and self-repair can be achieved. In particular, lost genes caused by faulty cells can be recovered through gene updating based on the remaining normal neighbor cells during the self-repair process. A reliability model of the proposed memory structure is built considering the gene updating method, and depending on the implementations of the memory, the hardware overhead is modeled. Based on the reliability model and hardware overhead model, we can find that the memory can achieve high reliability with relatively few gene backups and with low hardware overhead. Theoretical analysis and a simulation experiment show that the new genome memory structure not only achieves functional differentiation and self-repair of the embryonics array, but also ensures system reliability while reducing hardware overhead. This has significant value in engineering applications, allowing the proposed genome memory structure to be used to design larger scale self-repair chips.