Feature Size Reduction Research Articles

Design and analysis of a current mode integrated CTLE with charge mode adaptation

With the reduction in feature size of CMOS transistors, the off-chip link speeds have not increased in the same pace as the on-chip link speeds. This gap in speed demands for better interface circuitry to mitigate the adverse effects of the off-chip links, especially, the intersymbol interference due to limited channel bandwidth and reflections due to impedance discontinuities. In this work, a first current mode continuous time linear equalizer (CTLE) with charge mode pole-zero adaptation scheme is proposed. The proposed equalizer is realized with common gate (CG) topology using switched capacitor based pole-zero adaptation to suit varying channel characteristics. The input impedance of the CG-CTLE is made equal to the characteristic impedance of the off-chip link, eliminating the need for a separate resistive termination. Since the proposed CG-CTLE acts as the first stage of the current mode receiver, there is no need for a separate trans-impedance amplifier or a preamplifier. In addition, the proposed CG-CTLE is analytically compared with conventional common source (CS) CTLE for the same targeted output signal swing and power consumption. The CG-CTLE outperforms CS-CTLE in terms of bandwidth and SNR, and is supported by analysis and simulations. The proposed CG-CTLE is implemented in a 1.1V, 65-nm CMOS technology. The performance results show that it achieves a data rate of 15Gb/s while equalizing the loss of a 7.5 inch FR4 PCB trace. It also offers an input impedance of 44.6Ω, SNR of 23dB and a bandwidth of 7.575GHz and consumes a power of 13.9mW.

Semiconductor Memory Road Map: Advances in Semiconductor Memory

Since the creation of the integrated circuit (IC), the rapid reduction in feature size and increase in density known as Moore's law has enabled drastic cost and performance improvements, leading to advances in the entire IT industry, enabling the creation of PCs, smartphones, cloud services and ultra-thin televisions alike.

Manufacture and in vivo evaluation of laminated microchannel neural interfaces: do endoneurial basement membrane protein coatings enhance peripheral nerve regeneration through microchannels?

Event Abstract Back to Event Manufacture and in vivo evaluation of laminated microchannel neural interfaces: do endoneurial basement membrane protein coatings enhance peripheral nerve regeneration through microchannels? Henry Lancashire1*, Yazan Al-Ajam1, Catherine J. Pendegrass1*, Anne Vanhoestenberghe2*, Nick Donaldson3* and Gordon W. Blunn1 1 University College London, John Scales Centre for Biomedical Engineering, United Kingdom 2 University College London, Aspire Centre for Rehabilitation Engineering and Assistive Technologies, United Kingdom 3 University College London, Medical Physics & Biomedical Engineering, United Kingdom Introduction: Developing long-term neural interfaces for prosthetic control remains challenging[1]. Microchannel neural interfaces (MNIs) overcome some difficulties with neural recording: reducing microchannel diameter, increases recorded signal amplitude and selectivity[2],[3]. However, in vivo, small microchannels (< 50 μm ⌀) become obstructed by fibrous tissue[4]-[6]. Basement membrane (BM) protein coatings improve neural regeneration in vitro[7]. We hypothesise that coating the MNI lumen with BM protein will improve nerve regeneration. Materials and Methods: MNIs with 150 µm by 200 µm by 5 mm microchannels were prepared by bonding silicone and metal foil sheets[8] and coated with mixed BM proteins (10 µg/cm² Collagen-IV + 1 µg/cm² Laminin-2 + 175 ng/cm² Nidogen-1): the BM group. The control group was unmodified MNIs. In vivo procedures complied with the UK's Animals (Scientific Procedures) Act (1986 rev. 2013). Adult, male, Lewis rats (N=24) were randomised to 4 groups (n=6): 4 weeks BM; 4 weeks control; 8 weeks BM; 8 weeks control. MNIs were implanted by resecting the sciatic nerve, at mid-thigh. MNIs were secured using proximal and distal epineurial sutures (9-0 polyamide, S&T). Sciatic function index (SFI) was monitored weekly[9]. After 4 and 8 weeks MNIs were evaluated using wax histology[10]. Nerve morphometry immediately proximal and distal to MNIs was assessed. Results: A single animal was lost to follow-up (4 weeks control). SFI increased over 8 weeks in both groups (fig 1., p<0.001). There was no significant difference in SFI rate between groups, circa +0.57 units per day (p=0.9286). Distal axon diameters were greater in the control group at 4 weeks (p<0.001), and greater in the BM group at 8 weeks (fig 2, p<0.001). Axon density was greater proximal to MNIs in the control group and, greater distally in the BM group (not significant, p≥0.188). Control group electrode impedance fell significantly following implantation (p=0.01), but not in the BM group (p≥0.133). 1 kHz impedance was not significantly different between the groups at 4 or 8 weeks (p≥0.089). Discussion: There was no difference in functional recovery between control and BM groups. As with long nerve defects complete recovery was not observed[11]. Histology indicated frustrated axon growth in the control group, while BM encouraged axon growth through the MNI increasing distal axon densities. MNIs may act as nerve guides, directing axon regrowth. Axon density and diameter were lower than for healthy nerve. Axon diameters were similar to previous MNI studies[4], but smaller than non-resected nerve interfaces[12]. Conclusion: BM proteins did not noticeably improve outcomes; however, alternative MNI lumen coatings may improve nerve regeneration. We are now developing the next generation MNIs by increasing the open cross sectional area, reducing feature size, and including amplification and multiplexing. We would like to thank Gillian Hughes and Roberta Ferro de Godoy for assistance with the in vivo work.; We would like to thank Alexander Mosse and Elliot Magee for assistance with device manufacture.; HL would like to thank the EPSRC (UK) for funding through the M3S Doctoral Training Centre (EP/G036675/1) and the UCL Doctoral Prize Fellowship schemes.

Computational Intelligence Optimization Algorithm Based on Meta-heuristic Social-Spider: Case Study on CT Liver Tumor Diagnosis

Feature selection is an importance step in classification phase and directly affects the classification performance. Feature selection algorithm explores the data to eliminate noisy, redundant, irrelevant data, and optimize the classification performance. This paper addresses a new subset feature selection performed by a new Social Spider Optimizer algorithm (SSOA) to find optimal regions of the complex search space through the interaction of individuals in the population. SSOA is a new natural meta-heuristic computation algorithm which mimics the behavior of cooperative social-spiders based on the biological laws of the cooperative colony. Different combinatorial set of feature extraction is obtained from different methods in order to keep and achieve optimal accuracy. Normalization function is applied to smooth features between [0,1] and decrease gap between features. SSOA based on feature selection and reduction compared with other methods over CT liver tumor dataset, the proposed approach proves better performance in both feature size reduction and classification accuracy. Improvements are observed consistently among 4 classification methods. A theoretical analysis that models the number of correctly classified data is proposed using Confusion Matrix, Precision, Recall, and Accuracy. The achieved accuracy is 99.27%, precision is 99.37%, and recall is 99.19%. The results show that, the mechanism of SSOA provides very good exploration, exploitation and local minima avoidance.

FluidCheck

Soft errors have become a serious cause of concern with reducing feature sizes. The ability to accommodate complex, Simultaneous Multithreading (SMT) cores on a single chip presents a unique opportunity to achieve reliable execution, safe from soft errors, with low performance penalties. In this context, we present FluidCheck , a checker architecture that allows highly flexible assignment and migration of checking duties across cores. In this article, we present a mechanism to dynamically use the resources of SMT cores for checking the results of other threads, and propose a variety of heuristics for migration of such checker threads across cores. Secondly, to make the process of checking more efficient, we propose a set of architectural enhancements that reduce power consumption, decrease the length of the critical path, and reduce the load on the Network-on-Chip (NoC). Based on our observations, we design a 16 core system for running SPEC2006 based bag-of-tasks applications. Our experiments demonstrate that fully reliable execution can be attained with a mere 27% slowdown, surpassing traditional redundant threading based techniques by roughly 42%.

Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100nm near the transistors and 1000nm away from the transistors and near the solder bumps. In such BEOL stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers.This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data.

SPCM

Phase Change Memory (PCM) devices are one of the known promising technologies to take the place of DRAM devices with the aim of overcoming the obstacles of reducing feature size and stopping ever growing amounts of leakage power. In exchange for providing high capacity, high density, and nonvolatility, PCM Multilevel Cells (MLCs) impose high write energy and long latency. Many techniques have been proposed to resolve these side effects. However, read performance issues are usually left behind the great importance of write latency, energy, and lifetime. In this article, we focus on read performance and improve the critical path latency of the main memory system. To this end, we exploit striping scheme by which multiple lines are grouped and lie on a single MLC line array. In order to achieve more performance gain, an adaptive ordering mechanism is used to sort lines in a group based on their read frequency. This scheme imposes large energy and lifetime overheads due to its intensive demand for higher write bandwidth. Thus, we equipped our design with a grouping/pairing write queue to synchronize write-back requests such that all updates to an MLC array occur at once. The design is also augmented by a directional write scheme that takes benefits of the uniformity of accesses to the PCM device—caused by the large DRAM cache—to determine the writing mode (striped or nonstriped). This adaptation to write operations relaxes the energy and lifetime overheads. We improve the read latency of a 2-bit MLC PCM memory by more than 24% (and Instructions Per Cycle (IPC) by about 9%) and energy-delay product by about 20% for a small lifetime degradation of 8%, on average.

Fabrication of micron scale metallic structures on photo paper substrates by low temperature photolithography for device applications

Using commercial standard paper as a substrate has a significant cost reduction implication over other more expensive substrate materials by approximately a factor of 100 (Shenton et al 2015 EMRS Spring Meeting; Zheng et al 2013 Nat. Sci. Rep. 3 1786). Discussed here is a novel process which allows photolithography and etching of simple metal films deposited on paper substrates, but requires no additional facilities to achieve it. This allows a significant reduction in feature size down to the micron scale over devices made using more conventional printing solutions which are of the order of tens of microns. The technique has great potential for making cheap disposable devices with additional functionality, which could include flexibility and foldability, simple disposability, porosity and low weight requirements. The potential for commercial applications and scale up is also discussed.

Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects

Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects. Findings – It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely. Research limitations/implications – In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions. Practical implications – The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation. Originality/value – This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes.

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS’89 benchmark circuits show that our method is more accurate and efficient than previous methods.

Analytical modeling of read noise margin of a CNFET based 6T SRAM cell

There is a pressing need to increase the levels of on-chip integration of SRAM, which offers serious design challenges in terms of power requirement and cell stability. Static noise margin is an important criterion to constitute SRAM stability. As the CMOS technology is facing numerous challenges due to feature size reductions, carbon nanotube field effect transistors (CNFET) has been recommended for high stability, high performance and low power SRAM cell design. In this paper the stability of CNFET based 6T SRAM cells is investigated analytically as well as by simulation. We have derived an explicit analytical expression for the read static noise margin as a function of device parameters. The SRAM is also simulated in HSPICE and the results are in good agreement with the result obtained from the analytic expression. Along with other parameters supply voltage is also considered as a variable in the analytic expression to observe its effect on the read static noise margin.

Solvent vapor annealing of block copolymers in confined topographies: commensurability considerations for nanolithography.

The directed self-assembly of block copolymer (BCP) materials in topographically patterned substrates (i.e., graphoepitaxy) is a potential methodology for the continued scaling of nanoelectronic device technologies. In this Communication, an unusual feature size variation in BCP nanodomains under confinement with graphoepitaxially aligned cylinder-forming poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) BCP is reported. Graphoepitaxy of PS-b-P4VP BCP line patterns (CII ) is accomplished via topo-graphy in hydrogen silsequioxane (HSQ) modified substrates and solvent vapor annealing (SVA). Interestingly, reduced domain sizes in features close to the HSQ guiding features are observed. The feature size reduction is evident after inclusion of alumina into the P4VP domains followed by pattern transfer to the silicon substrate. It is suggested that this nano-domain size perturbation is due to solvent swelling effects during SVA. It is proposed that using a commensurability value close to the solvent vapor annealed periodicity will alleviate this issue leading to uniform nanofins.

Development of 2.5D and 3D IC Fabrication and Assembly Technologies

2.5D/3D IC assembly is where the traditional foundry and assembly house model breaks down. The greatly reduced feature sizes of microbumps in combination with very large, thin interposers and ICs present many challenges for assembly. With densely integrated packages and stacked thin dies, warpage at various steps of assembly process can lead to die crack, weak or open interconnection, and delamination. Microbump die with copper pillar and solder cap lacks the flexibility of conventional BGA solder balls in warpage compensation. Low temperature dielectric materials for interposer backside passivation lack chemical, thermal stability and mechanical strength compared to similar materials cured at higher temperatures. Ultra- low stand-off between dies creates new challenge for flux residue removal and underfill processing, adhesion and reliability. In this paper, we present learning and results from building two Invensas 2.5D interposer test vehicles with rectangular (19mmx27mm) and square (24mmx24 mm) silicon interposers. Since the industry is still debating where the MEOL processes will take place, these two test vehicles use both assembly centric and fab centric flows. We conducted comprehensive material and process compatibility studies to meet our goal of process capability and product reliability. We explored three different interposer fabrication/ assembly flows that includes copper-to-copper bonding as well as solder capped copper pillar microbumps for microbump die to interposer connection. We optimized the interposer fabrication process to improve interposer quality and warpage. We instituted 100% bump inspection and tight control on microbump die quality and co-planarity to improve assembly yield. We developed robust soldering and cleaning processes to achieve high soldering process yield. We evaluated several methods of flux clean and developed a procedure to achieve optimal flux residue removal without causing mechanical damage to solder joints. We explored vacuum and pressure curing process for underfill and adopted advance underfill cure technology to eliminate voids in underfill. The impact of these factors on assembly yield and reliability will be presented.

Chemical Mechanical Planarization: Advanced Material and Consumable Challenges

The unprecedented and continuing increase in the computational power and functionality of microelectronic devices, extending beyond more-than-Moore, are driven by the ever shrinking dimensions of logic and memory circuits, now numbering over a billion and half, all packed into an area of ∼15 cm2. As the costs of these devices drop, they have become ubiquitous across the world, from high performance computing to smart phones to driverless cars to children’s toys. The most common substrate for these devices continues to be Si and the process sequence used to fabricate these devices is frequently divided into front-end-of-the-line (FEOL) and back-end-of-the-line (BEOL) processes, each with its own peculiar technological and manufacturing yield challenges. Once all the active circuit elements are fabricated in the Si substrate using FEOL processes, they need to be interconnected and also connected to an external power source to become functional. While new materials continue to be incorporated at various levels into the processing sequence, copper remains the metal of choice for the interconnect wiring which is created using BEOL processes. The Cu wiring itself is electrically insulated by a low-k dielectric and protected by a diffusion barrier layer that can also act as an adhesion promoter and, depending on its electrical conductivity, enable direct electroplating of Cu. The characteristics of the low-k dielectric and the barrier layer have an immense influence on the manufacturing process sequence as well as the performance and long term reliability of the devices. Significant advances continue to be made in identifying newer sets of materials to fill these roles, especially for the narrower Cu lines where the space for the liner is limited, along with the associated processing steps. While advances in lithographic techniques facilitated the feature size reduction that has already reached 14 nm in high volume commercial production and seemingly headed lower, the same advances in lithography also demand ever more stringent surface planarity requirements, both locally across the chip and more globally across the entire wafer. Chemical mechanical planarization (CMP) is the only technique that has so far been capable of achieving these demanding requirements at the large volume manufacturing level in spite of it being a counter intuitive process that is prone to non-uniform material removal, defects and contamination caused by pad debris, by the billions of abrasive particles contacting the wafer surface and by the host of reactive and nonreactive chemicals used in the planarization process. Mitigating such yield-diminishing factors is one of the major challenges driving the advances in CMP technology and led to improvements in the polisher components like wafer carrier, slurry delivery system, retainer ring, backing film, etc., as well as all the other consumables including polishing pads, conditioners, and polishing slurries. Given the heterogeneity and pattern density and feature size variations of the films being planarized on the wafer surface, process

Nature-inspired feature subset selection application to arabic speaker recognition system

Feature selection is an important task which can affect the performance of pattern classification and recognition system. This study uses two nature-inspired algorithms, namely genetic algorithms and particle swarm optimization, for this problem. The algorithms adopt classifier performance and the number of the selected features as heuristic information, and select the optimal feature subset in terms of feature set size and classification performance. From experimental results, the major contribution of this work are: the reduction of vector feature size without loosing performance which is crucial for real time application and low-resources devices as well as the time needed to find the optimal subset features compared to exhaustive search or other conventional methods (less than 50 iterations instead of billions of iterations to test all possible configurations).

Power Optimization for ASIC Design (Low power ASIC)

The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce feature size. Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. However, questions regarding the limits of scaling have arisen in recent years due to the presence of leakage. As the supply voltage is lowered to satisfy the performance requirement, the threshold voltage has to be scaled, which increases leakage. More than 40% of the total power consumption is due to leakage of the transistor is in DSM. This leakage will increase with scaling become comparable with switching power. The goal of this paper is to analyse different low power circuits and optimization techniques to improve the power dissipation with the use of power gating components, retention registers, level shifters, isolation cells etc.

Low Energy Signal Processing Techniques for Reliability Improvement of High-Density NAND Flash Memory

High density NAND flash memory employs very fine process technology, such as sub-20 nm process, and multi-level cell data coding. The reduced feature size not only lowers the number of electrons stored at each floating-gate but also increases the cell-to-cell interference (CCI). As a result, the reliability of NAND flash memory has become an important issue that cannot be well solved by only advancing the process technology. In this paper, we present signal processing and error correction techniques that can overcome the reliability problem while minimizing the energy consumption. These techniques include efficient estimation of the threshold voltage distribution, CCI cancellation aware soft-information computation, and low-energy soft-decision error correction. We also include experimental results for the presented techniques.

Necessity of Cleaning and its Application in Future Memory Devices

Concerning the processes of the semiconductor industry, device integration is increasing and cell structure is becoming more complicated, which brings many new kinds of challenges. The basic requirements for a future integration device are minimum feature size reduction with device integration and high-speed operation with sufficient cell capacitance. Many kinds of conventional films including electrode and dielectric materials should be altered to meet device requirements. Moreover, as the allowance level for contaminants on substrate surfaces becomes more stringent, the importance of removing them becomes even greater. Because of this, the semiconductor process for high quality device fabrication will never be realized without perfect cleaning on all surfaces. It is reported that the conventional cleaning solutions such as a NH4OH/H2O2/H2O (SC-1) solution (1:4:20, 80 °C), H2SO4/H2O2 (SPM) solution (4:1, 90 to 120°C), and HCl/H2O2/H2O (HPM) solution (1:1:6, 80 to 90°C) are not compatible with metal film exposed surfaces with very tiny patterns, due to the fast etching rate of metal films [1] . In 1995, at the base of the mechanism of the removal of the adhered contaminants such as metallic impurities, particles and organics, T. Ohmi proposed a total room temperature wet cleaning process (so called “UCT cleaning”) [2]. As a result of the continuous research on developed cleaning, the five steps process was revised to a four step room temperature wet cleaning for real device cleaning. The cleaning consists of 1) CO2 added O3-UPW cleaning for removing organic and metallic impurities, 2) NH3 added H2-UPW+MS cleaning for removing of particles, 3) HF/H2O2(FPM) cleaning for removing metallic impurities, and 4) H2-UPW+MS rinse for the removal of chemical residues, prevention of particle re-adhesion, suppression of native oxide growth, and enhancement of H-termination.

Tunable daughter molds from a single Si master grating mold

After the cost of ownership of tool, the next significant cost involved in nanoimprint lithography is that of mold fabrication. The cost of mold fabrication is proportional to the area of pattern and follows an inverse relationship with the pattern resolution. In this work, the authors demonstrate proof-of-concept fabrication of Si and SiO2 grating molds of variable feature sizes, spacings, densities, and aspect ratios that can be generated from a single Si master mold of 2 μm line and space features. This process utilizes “SiO2 resin,” which can be imprinted via in situ thermal free radical polymerization. Heat-treatment of the patterned resin resulted in loss of organics, formation of SiOx and gave rise to known feature size reduction (∼65%). After the pattern transfer using SiOx as the etch mask, a Si daughter mold containing 0.7 μm wide gratings with 3.3 μm spacing was generated. The process of imprinting and heat-treatment was repeated using the daughter mold, which regenerated a mold that approximates the master mold feature profile. Our technique demonstrates that submicron-sized features can be achieved from Si molds containing micron-sized features and vice versa. Such flexibility may lead to substantial reduction in the cost of mold fabrication.

Self-controlled fabrication of single-crystalline silicon nanobeams using conventional micromachining

This paper reports on a low-cost top-down approach to the nano-precision fabrication of nanobeams on single-crystalline silicon using only conventional micromachining technology. The fabrication technique takes advantage of the crystalline structure of silicon for controllable feature size reduction of nanobeams with atomically smooth surfaces and sharp edges. Applying a deliberate rotational misalignment in a 2 μm resolution standard lithography process, followed by anisotropic wet etching of the silicon, nanobeams with well uniform widths as small as ∼85 nm are fabricated on thin SOI substrates. As a proof of concept for the incorporation of such nanobeams within electromechancial structures, we successfully demonstrate thermally actuated resonators that show very high frequencies (close to 50 MHz).